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Fix missing sync of timer ENABLE bit #795

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merged 2 commits into from
Dec 5, 2024
Merged

Fix missing sync of timer ENABLE bit #795

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189956b
Fix missing sync of timer ENABLE bit
fko-kuptec Dec 3, 2024
fb07c3b
Merge branch 'master' into fix-tc-enable-sync
jbeaurivage Dec 5, 2024
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12 changes: 12 additions & 0 deletions hal/src/peripherals/pwm/d11.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@ impl $TYPE {
count.ctrla().write(|w| w.swrst().set_bit());
while count.ctrla().read().bits() & 1 != 0 {}
count.ctrla().modify(|_, w| w.enable().clear_bit());
while count.status().read().syncbusy().bit_is_set() {}
count.ctrla().modify(|_, w| {
match params.divider {
1 => w.prescaler().div1(),
Expand All @@ -48,6 +49,7 @@ impl $TYPE {
count.cc(0).write(|w| unsafe { w.cc().bits(params.cycles as u16) });
count.cc(1).write(|w| unsafe { w.cc().bits(0) });
count.ctrla().modify(|_, w| w.enable().set_bit());
while count.status().read().syncbusy().bit_is_set() {}

Self {
clock_freq: clock.freq(),
Expand All @@ -60,6 +62,7 @@ impl $TYPE {
let params = TimerParams::new(period, self.clock_freq);
let count = self.tc.count16();
count.ctrla().modify(|_, w| w.enable().clear_bit());
while count.status().read().syncbusy().bit_is_set() {}
count.ctrla().modify(|_, w| {
match params.divider {
1 => w.prescaler().div1(),
Expand All @@ -74,6 +77,7 @@ impl $TYPE {
}
});
count.ctrla().modify(|_, w| w.enable().set_bit());
while count.status().read().syncbusy().bit_is_set() {}
count.cc(0).write(|w| unsafe { w.cc().bits(params.cycles as u16) });
}

Expand Down Expand Up @@ -109,11 +113,13 @@ impl $crate::ehal_02::PwmPin for $TYPE {
fn disable(&mut self) {
let count = self.tc.count16();
count.ctrla().modify(|_, w| w.enable().clear_bit());
while count.status().read().syncbusy().bit_is_set() {}
}

fn enable(&mut self) {
let count = self.tc.count16();
count.ctrla().modify(|_, w| w.enable().set_bit());
while count.status().read().syncbusy().bit_is_set() {}
}

fn get_duty(&self) -> Self::Duty {
Expand Down Expand Up @@ -188,6 +194,7 @@ impl $TYPE {
tcc.ctrlbclr().write(|w| w.dir().set_bit() );
while tcc.syncbusy().read().ctrlb().bit_is_set() {}
tcc.ctrla().modify(|_, w| w.enable().clear_bit());
while tcc.syncbusy().read().enable().bit_is_set() {}
tcc.ctrla().modify(|_, w| {
match params.divider {
1 => w.prescaler().div1(),
Expand All @@ -206,6 +213,7 @@ impl $TYPE {
tcc.per().write(|w| unsafe { w.bits(params.cycles as u32) });
while tcc.syncbusy().read().per().bit_is_set() {}
tcc.ctrla().modify(|_, w| w.enable().set_bit());
while tcc.syncbusy().read().enable().bit_is_set() {}
}

Self {
Expand All @@ -222,10 +230,12 @@ impl $crate::ehal_02::Pwm for $TYPE {

fn disable(&mut self, _channel: Self::Channel) {
self.tcc.ctrla().modify(|_, w| w.enable().clear_bit());
while self.tcc.syncbusy().read().enable().bit_is_set() {}
}

fn enable(&mut self, _channel: Self::Channel) {
self.tcc.ctrla().modify(|_, w| w.enable().set_bit());
while self.tcc.syncbusy().read().enable().bit_is_set() {}
}

fn get_period(&self) -> Self::Time {
Expand Down Expand Up @@ -257,6 +267,7 @@ impl $crate::ehal_02::Pwm for $TYPE {
let period = period.into();
let params = TimerParams::new(period, self.clock_freq);
self.tcc.ctrla().modify(|_, w| w.enable().clear_bit());
while self.tcc.syncbusy().read().enable().bit_is_set() {}
self.tcc.ctrla().modify(|_, w| {
match params.divider {
1 => w.prescaler().div1(),
Expand All @@ -271,6 +282,7 @@ impl $crate::ehal_02::Pwm for $TYPE {
}
});
self.tcc.ctrla().modify(|_, w| w.enable().set_bit());
while self.tcc.syncbusy().read().enable().bit_is_set() {}
self.tcc.per().write(|w| unsafe { w.bits(params.cycles as u32) });
while self.tcc.syncbusy().read().per().bit() {}
}
Expand Down
8 changes: 8 additions & 0 deletions hal/src/peripherals/pwm/d5x.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -156,6 +156,7 @@ impl<I: PinId> $TYPE<I> {
count.ctrla().write(|w| w.swrst().set_bit());
while count.ctrla().read().bits() & 1 != 0 {}
count.ctrla().modify(|_, w| w.enable().clear_bit());
while count.syncbusy().read().enable().bit_is_set() {}
count.ctrla().modify(|_, w| {
match params.divider {
1 => w.prescaler().div1(),
Expand All @@ -175,6 +176,7 @@ impl<I: PinId> $TYPE<I> {
count.cc(1).write(|w| unsafe { w.cc().bits(0) });
while count.syncbusy().read().cc1().bit_is_set() {}
count.ctrla().modify(|_, w| w.enable().set_bit());
while count.syncbusy().read().enable().bit_is_set() {}

Self {
clock_freq: clock.freq(),
Expand All @@ -196,6 +198,7 @@ impl<I: PinId> $TYPE<I> {
let params = TimerParams::new(period, self.clock_freq);
let count = self.tc.count16();
count.ctrla().modify(|_, w| w.enable().clear_bit());
while count.syncbusy().read().enable().bit_is_set() {}
count.ctrla().modify(|_, w| {
match params.divider {
1 => w.prescaler().div1(),
Expand All @@ -210,6 +213,7 @@ impl<I: PinId> $TYPE<I> {
}
});
count.ctrla().modify(|_, w| w.enable().set_bit());
while count.syncbusy().read().enable().bit_is_set() {}
count.cc(0).write(|w| unsafe { w.cc().bits(params.cycles as u16) });
while count.syncbusy().read().cc0().bit_is_set() {}
}
Expand Down Expand Up @@ -239,11 +243,13 @@ impl<I: PinId> $crate::ehal_02::PwmPin for $TYPE<I> {
fn disable(&mut self) {
let count = self.tc.count16();
count.ctrla().modify(|_, w| w.enable().clear_bit());
while count.syncbusy().read().enable().bit_is_set() {}
}

fn enable(&mut self) {
let count = self.tc.count16();
count.ctrla().modify(|_, w| w.enable().set_bit());
while count.syncbusy().read().enable().bit_is_set() {}
}


Expand Down Expand Up @@ -573,6 +579,7 @@ impl<I: PinId, M: PinMode> $TYPE<I, M> {
tcc.ctrlbclr().write(|w| w.dir().set_bit() );
while tcc.syncbusy().read().ctrlb().bit_is_set() {}
tcc.ctrla().modify(|_, w| w.enable().clear_bit());
while tcc.syncbusy().read().enable().bit_is_set() {}
tcc.ctrla().modify(|_, w| {
match params.divider {
1 => w.prescaler().div1(),
Expand All @@ -591,6 +598,7 @@ impl<I: PinId, M: PinMode> $TYPE<I, M> {
tcc.per().write(|w| unsafe { w.bits(params.cycles as u32) });
while tcc.syncbusy().read().per().bit_is_set() {}
tcc.ctrla().modify(|_, w| w.enable().set_bit());
while tcc.syncbusy().read().enable().bit_is_set() {}

Self {
clock_freq: clock.freq(),
Expand Down
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