adding rev3 base FW

configs/Cornell_rev3_p1_VU13p-1-SM_USP/Generate_svf.tcl

@@ -0,0 +1,34 @@
+#this has to be called from inside an open session
+source ${apollo_root_path}/configs/${build_name}/settings.tcl
+
+set SVF_TARGET [format "svf_top%06u" [expr {round(1000000 *rand())}]]
+
+
+
+#derived from walkthrough https://blog.xjtag.com/2016/07/creating-svf-files-using-xilinx-vivado/
+open_hw
+if { [string length [get_hw_targets -quiet -regexp .*/${SVF_TARGET}] ]  } {
+  delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]
+}
+create_hw_target ${SVF_TARGET}
+close_hw_target
+open_hw_target [get_hw_targets -regexp .*/${SVF_TARGET}]
+
+
+#1st in chain, no need to add another FPGA to the chain
+
+#add the virtex to the chain
+set DEVICE [create_hw_device -part ${FPGA_part}]
+set_property PROGRAM.FILE ${apollo_root_path}/bit/top_${build_name}.bit $DEVICE
+set_param xicom.config_chunk_size 0
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
+
+#2nd chain
+create_hw_device -part xcvu13p-flga2577-1-e
+
+program_hw_devices -force -svf_file ${apollo_root_path}/bit/top_${build_name}.svf ${DEVICE}
+
+write_cfgmem -force -interface spix4 -loadbit "up 0 ${apollo_root_path}/bit/top_${build_name}.bit" -format mcs -size 128 -file "${apollo_root_path}/bit/top_${build_name}.mcs"
+
+delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]

configs/Cornell_rev3_p1_VU13p-1-SM_USP/files.tcl

@@ -0,0 +1,50 @@
+set bd_path proj
+
+array set bd_files [list {c2cSlave} {src/CM_yaml/CM_C2C/createC2CSlaveInterconnect.tcl} \
+			]
+
+set vhdl_files "\
+     configs/${build_name}/src/top.vhd \
+     src/misc/DC_data_CDC.vhd \
+     src/misc/pacd.vhd \
+     src/misc/types.vhd \
+     src/misc/capture_CDC.vhd \
+     src/misc/counter.vhd \
+     src/misc/counter_CDC.vhd \
+     regmap_helper/axiReg/axiRegWidthPkg_32.vhd \
+     regmap_helper/axiReg/axiRegPkg_d64.vhd \
+     regmap_helper/axiReg/axiRegPkg.vhd \
+     regmap_helper/axiReg/axiReg.vhd \
+     regmap_helper/axiReg/bramPortPkg.vhd \
+     regmap_helper/axiReg/axiRegBlocking.vhd \
+     src/C2C_INTF/C2C_Intf.vhd \
+     src/C2C_INTF/CM_phy_lane_control.vhd \
+     src/RGB_PWM.vhd \
+     src/LED_PWM.vhd \
+     src/misc/rate_counter.vhd \
+     src/CM_FW_info/CM_FW_info.vhd \
+     ${autogen_path}/IO/IO_PKG.vhd \
+     ${autogen_path}/IO/IO_map.vhd \
+     ${autogen_path}/C2C_INTF/C2C_INTF_map.vhd \
+     ${autogen_path}/C2C_INTF/C2C_INTF_PKG.vhd \
+     ${autogen_path}/CM_FW_INFO/CM_FW_INFO_PKG.vhd \
+     ${autogen_path}/CM_FW_INFO/CM_FW_INFO_map.vhd \
+     src/C2C_INTF/picoblaze/picoblaze/kcpsm6.vhd \
+     src/C2C_INTF/picoblaze/uart_rx6.vhd \
+     src/C2C_INTF/picoblaze/uart_tx6.vhd \
+     src/C2C_INTF/picoblaze/uC.vhd \
+     src/C2C_INTF/picoblaze/picoblaze/cli.vhd \
+     "
+set xdc_files "\
+    configs/${build_name}/src/top_pins.xdc \
+    configs/${build_name}/src/top_timing.xdc	\
+    "	    
+
+set xci_files "\
+	      cores/AXI_BRAM/AXI_BRAM.xci \
+	      cores/DP_BRAM/DP_BRAM.xci \
+    	      "
+
+set include_files "\
+    		  src/i2cAXIMaster/files.tcl	\
+		  "		  

configs/Cornell_rev3_p1_VU13p-1-SM_USP/settings.tcl

@@ -0,0 +1,19 @@
+
+#set the FPGA part number
+set FPGA_part xcvu13p-flga2577-1-e
+
+##for c2c
+set C2C F1_C2C
+set C2C_PHY ${C2C}_PHY
+set C2CB F1_C2CB
+set C2CB_PHY ${C2CB}_PHY
+
+#create remote device tree entries, 64 bit
+global REMOTE_C2C_64
+set REMOTE_C2C_64 1
+
+
+set top top
+
+set outputDir ./
+