Add an RFC for Print statement and string formatting.

[wanda-phi]

Rendered

[whitequark]

We have discussed this RFC on the 2024-03-04 weekly meeting. The disposition was to merge, with the following changes:

• Clarify that the first character of a string is stored in the least significant bits of a string (which is the inverse of what Verilog does).
• Define __format__ on Value to prevent unintentional misuse of f-strings that will not result in the desired effect (it will insert the AST dump instead of the runtime value into the string).

[lekcyjna123]

Hi,
in "Future possibilities" you have pointed to:

• Some kind of output redirection or output hook could be implemented in pysim.
• Likewise, a hook for assertion failure could be desirable.
• Some way to print the current simulation time could be useful.

Maybe you will be interested in kuznia-rdzeni/coreblocks#595 where we have recently added logging possibility with syntax similar to the python logging library. There is integration with pysim and cocotb simulators. The printing is handled in separate simulation process so we have a possibility to inject custom callable on having error print. There is also simulation time printed.

The code is not very strictly bound to the transactron framework. Only the DependencyContext is used (something like global variable), so I think that it can be possible to integrate our solution with Amaranth if you wish.

@tilk @xThaid please look on this RFC and RFC 58.

[whitequark]

Note that Print is designed to be synthesizable so that it can also be used with CXXRTL or exported to Verilog for use with Verilator, etc. It is explicitly not desired to introduce features that would only be implementable in a Python simulation but not in these other contexts.

In light of this, I think your logging functionality would probably need to reserve the beginning of the string for metadata, which can be then filtered by means of capturing and processing the output.