Merge pull request chipsalliance#3982 from alainmarcel/preproc_fix

Preprocessor fix for escaped identifiers
alainmarcel · Sep 11, 2024 · fbbe26e · fbbe26e
2 parents 5f6e20e + ccf1116
commit fbbe26e
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Showing 3 changed files with 8 additions and 11 deletions.
diff --git a/grammar/SV3_1aPpLexer.g4 b/grammar/SV3_1aPpLexer.g4
@@ -16,7 +16,10 @@
 
 lexer grammar SV3_1aPpLexer;
 
-ESCAPED_IDENTIFIER: '\\' ~[WS\r\t\n]*? WS;
+ESCAPED_IDENTIFIER: '\\' ~[WS\r\t\n]*? WS |
+                    '\\' ( OPEN_BRACKET? [A-Za-z0-9_$+-.]+ CLOSE_BRACKET?)* WS;
+
+
 
 // A.9.2 Comments
 

diff --git a/grammar/build.xml b/grammar/build.xml
@@ -24,9 +24,9 @@ limitations under the License.
 
   <!-- set global properties for this build -->
   <property name="antlr_test_tool_location"
-	    value="../third_party/antlr4/antlr4-4.9.3-complete.jar"/>
+	    value="../third_party/antlr4_bin/antlr-4.12.0-complete.jar"/>
   <property name="antlr_tool_location"
-	    value="../third_party/antlr4/antlr4-4.9.3-complete.jar"/>
+	    value="../third_party/antlr4_bin/antlr-4.12.0-complete.jar"/>
   <property name="antlr_tool_target"  value="org.antlr.v4.Tool"/>
   <property name="antlr_test_rig"     value="org.antlr.v4.gui.TestRig"/>
   <property name="sv_parser_grammar"  value="SV3_1a"/>

diff --git a/third_party/tests/Yosys/Yosys.log b/third_party/tests/Yosys/Yosys.log
@@ -993,14 +993,8 @@ Processing: -cd various +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -ti
 [WARNING] : 0
 [   NOTE] : 0
 Processing: -cd various +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns shregmap.v -l shregmap.v.log
-[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/various/shregmap.v:15:7: Syntax error: no viable alternative at input 'module \',
-module \$__SHREG_DFF_P_ (input C, D, output Q);
-       ^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/various/shregmap.v:15:7:.
-[SNT:PA0207] ${SURELOG_DIR}/third_party/tests/Yosys/various/shregmap.v:19: Syntax error: mismatched input 'always' expecting <EOF>,
-always @(posedge C) 
-^-- ${SURELOG_DIR}/build/regression/Yosys/slpp_all/lib/work/various/shregmap.v:19:0:.
 [  FATAL] : 0
-[ SYNTAX] : 2
+[ SYNTAX] : 0
 [  ERROR] : 0
 [WARNING] : 0
 [   NOTE] : 0
@@ -1800,7 +1794,7 @@ Processing: -cd simple +incdir+. -parse -nocache -nobuiltin -nonote -noinfo -tim
 [   NOTE] : 0
 Processed 253 tests.
 [  FATAL] : 0
-[ SYNTAX] : 16
+[ SYNTAX] : 14
 [  ERROR] : 3
 [WARNING] : 230
 [   NOTE] : 0