Removed default slave value for all Slave AHB classes

Signed-off-by: Anderson Ignacio da Silva <[email protected]>
aignacio · Sep 9, 2024 · e3b8c5d · e3b8c5d
1 parent eb2baf4
commit e3b8c5d
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Showing 11 changed files with 29 additions and 37 deletions.
diff --git a/README.md b/README.md
@@ -276,7 +276,6 @@ class AHBLiteSlave:
         bus: AHBBus,
         clock: str,
         reset: str,
-        def_val: Union[int, str] = "Z",
         bp: Generator[int, None, None] = None,
         name: str = "ahb_lite",
         reset_act_low: bool = True,
@@ -304,7 +303,6 @@ class AHBLiteSlaveRAM(AHBLiteSlave):
         bus: AHBBus,
         clock: str,
         reset: str,
-        def_val: Union[int, str] = "Z",
         bp: Generator[int, None, None] = None,
         name: str = "ahb_lite_ram",
         mem_size: int = 1024,
@@ -380,7 +378,6 @@ async def run_test(dut):
         AHBBus.from_prefix(dut, "master"),
         dut.hclk,
         dut.hresetn,
-        def_val=0,
         bp=bp_fn,
         mem_size=mem_size_kib * 1024,
     )

diff --git a/cocotbext/ahb/ahb_monitor.py b/cocotbext/ahb/ahb_monitor.py
@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 27.10.2023
-# Last Modified Date: 07.09.2024
+# Last Modified Date: 09.09.2024
 import cocotb
 import logging
 import random
@@ -152,7 +152,14 @@ async def _monitor_recv(self):
             if first_st["phase"] == "addr":
                 self._check_signals(first_txn)
 
-                if self.bus.hready.value == 1:
+                if self.bus.hready.value == 0:
+                    raise AssertionError(
+                        f"[{self.bus.name}/{self.name}] AHB PROTOCOL VIOLATION:"
+                        "A slave cannot request that the address phase is extended"
+                        "and therefore all slaves must be capable of sampling the address during this time"
+                        " - ARM IHI 0033B.b (ID102715) - Section 1.3"
+                    )
+                else:
                     first_st["phase"] = "data"
 
     def _check_inputs(self) -> bool:

diff --git a/cocotbext/ahb/ahb_slave.py b/cocotbext/ahb/ahb_slave.py
@@ -29,7 +29,6 @@ def __init__(
         bus: AHBBus,
         clock: str,
         reset: str,
-        def_val: Union[int, str] = "Z",
         bp: Generator[int, None, None] = None,
         name: str = "ahb_lite",
         reset_act_low: bool = True,
@@ -39,7 +38,6 @@ def __init__(
         self.clk = clock
         self.rst = reset
         self.rst_act_low = reset_act_low
-        self.def_val = def_val
         self.bp = bp
         self.log = logging.getLogger(
             f"cocotb.{name}.{bus._name}." f"{bus._entity._name}"
@@ -56,14 +54,9 @@ def __init__(
 
     def _init_bus(self) -> None:
         """Initialize the bus with default value."""
-        for signal in self.bus._signals:
-            if signal in ["hready", "hresp", "hrdata"]:
-                sig = getattr(self.bus, signal)
-                try:
-                    default_value = self._get_def(len(sig))
-                    sig.setimmediatevalue(default_value)
-                except AttributeError:
-                    pass
+        self.bus.hready.setimmediatevalue(1)
+        self.bus.hresp.setimmediatevalue(AHBResp.OKAY)
+        self.bus.hrdata.setimmediatevalue(0)
 
     def _get_def(self, width: int = 1) -> BinaryValue:
         """Return a handle obj with the default value"""
@@ -79,7 +72,8 @@ async def _proc_txn(self):
         txn_size = AHBSize.WORD
         txn_type = AHBWrite.READ
 
-        self.bus.hrdata.value = self._get_def(len(self.bus.hrdata))
+        self.bus.hrdata.value = 0
+
         while True:
             # Wait for a txn
             await RisingEdge(self.clk)
@@ -88,7 +82,7 @@ async def _proc_txn(self):
             cur_hresp = copy.deepcopy(self.bus.hresp.value)
 
             # Default values in case there is no txn
-            self.bus.hready.value = 1  # self._get_def(1)
+            self.bus.hready.value = 1
             self.bus.hresp.value = AHBResp.OKAY
 
             if self.bp is not None:
@@ -129,7 +123,7 @@ async def _proc_txn(self):
             else:
                 if rd_start and cur_hready:
                     rd_start = False
-                    self.bus.hrdata.value = self._get_def(len(self.bus.hrdata))
+                    self.bus.hrdata.value = 0
 
                 if wr_start and cur_hready:
                     wr_start = False
@@ -242,13 +236,12 @@ def __init__(
         bus: AHBBus,
         clock: str,
         reset: str,
-        def_val: Union[int, str] = "Z",
         bp: Generator[int, None, None] = None,
         name: str = "ahb_lite_ram",
         mem_size: int = 1024,
         **kwargs,
     ):
-        super().__init__(bus, clock, reset, def_val, bp, name, **kwargs)
+        super().__init__(bus, clock, reset, bp, name, **kwargs)
         self.memory = Memory(size=mem_size)
 
     def _chk_rd(self, addr: int, size: AHBSize) -> bool:
@@ -405,9 +398,8 @@ def __init__(
         bus: AHBBus,
         clock: str,
         reset: str,
-        def_val: Union[int, str] = "Z",
         bp: Generator[int, None, None] = None,
         name: str = "ahb_slave",
         **kwargs,
     ):
-        super().__init__(bus, clock, reset, def_val, bp, name, **kwargs)
+        super().__init__(bus, clock, reset, bp, name, **kwargs)
diff --git a/cocotbext/ahb/version.py b/cocotbext/ahb/version.py
@@ -1 +1 @@
-__version__ = "0.3.7"
+__version__ = "0.3.8"
diff --git a/tests/test_ahb.py b/tests/test_ahb.py
@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 08.10.2023
-# Last Modified Date: 29.11.2023
+# Last Modified Date: 09.09.2024
 
 import cocotb
 import os
@@ -60,7 +60,7 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
     )
 
     ahb_slave = AHBSlave(
-        AHBBus.from_entity(dut), dut.hclk, dut.hresetn, def_val=0, bp=bp_fn
+        AHBBus.from_entity(dut), dut.hclk, dut.hresetn, bp=bp_fn
     )
 
     type(ahb_slave)

diff --git a/tests/test_ahb_lite.py b/tests/test_ahb_lite.py
@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 08.10.2023
-# Last Modified Date: 14.06.2024
+# Last Modified Date: 09.09.2024
 
 import cocotb
 import os
@@ -71,7 +71,7 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
     )
 
     ahb_lite_slave = AHBLiteSlave(
-        AHBBus.from_entity(dut), dut.hclk, dut.hresetn, def_val=0, bp=bp_fn
+        AHBBus.from_entity(dut), dut.hclk, dut.hresetn, bp=bp_fn
     )
 
     type(ahb_lite_slave)

diff --git a/tests/test_ahb_lite_log.py b/tests/test_ahb_lite_log.py
@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 08.10.2023
-# Last Modified Date: 02.09.2024
+# Last Modified Date: 09.09.2024
 
 import cocotb
 import os
@@ -62,7 +62,7 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
     )
 
     ahb_lite_slave = AHBLiteSlave(
-        AHBBus.from_entity(dut), dut.hclk, dut.hresetn, def_val=0, bp=bp_fn
+        AHBBus.from_entity(dut), dut.hclk, dut.hresetn, bp=bp_fn
     )
 
     type(ahb_lite_slave)

diff --git a/tests/test_ahb_lite_monitor_scoreboard.py b/tests/test_ahb_lite_monitor_scoreboard.py
@@ -3,7 +3,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 08.10.2023
-# Last Modified Date: 15.06.2024
+# Last Modified Date: 09.09.2024
 
 import cocotb
 import os
@@ -145,7 +145,6 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
         AHBBus.from_entity(dut),
         dut.hclk,
         dut.hresetn,
-        def_val=0,
         bp=bp_fn,
         mem_size=mem_size_kib * 1024,
     )

diff --git a/tests/test_ahb_lite_sram.py b/tests/test_ahb_lite_sram.py
@@ -3,7 +3,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 08.10.2023
-# Last Modified Date: 18.06.2024
+# Last Modified Date: 09.09.2024
 
 import cocotb
 import os
@@ -80,7 +80,6 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
         AHBBus.from_entity(dut),
         dut.hclk,
         dut.hresetn,
-        def_val=0,
         bp=bp_fn,
         mem_size=mem_size_kib * 1024,
     )

diff --git a/tests/test_ahb_lite_sram_all_sizes.py b/tests/test_ahb_lite_sram_all_sizes.py
@@ -3,7 +3,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 08.10.2023
-# Last Modified Date: 25.12.2023
+# Last Modified Date: 09.09.2024
 
 import cocotb
 import os
@@ -74,7 +74,6 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
         AHBBus.from_entity(dut),
         dut.hclk,
         dut.hresetn,
-        def_val=0,
         bp=bp_fn,
         mem_size=mem_size_kib * 1024,
     )

diff --git a/tests/test_ahb_lite_sram_no_errors.py b/tests/test_ahb_lite_sram_no_errors.py
@@ -3,7 +3,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <[email protected]>
 # Date              : 08.10.2023
-# Last Modified Date: 29.11.2023
+# Last Modified Date: 09.09.2024
 
 import cocotb
 import os
@@ -66,7 +66,6 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
         AHBBus.from_entity(dut),
         dut.hclk,
         dut.hresetn,
-        def_val=0,
         bp=bp_fn,
         mem_size=mem_size_kib * 1024,
     )