Emphasise that read_verilog doesn't lint #4705
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Link to verilator in the introduction. Include `verilator --lint-only fifo.v` in the example synth doc. Fix linter warnings in fifo.v.
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What's the relation to the docs change? Is this to make verilator linting happy?
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Yeah verilator gave lint warnings so I figured it was easy enough to fix them (and this wasn't a guided tutorial of how to fix it yourself)
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Although it does make the first image slightly more complex
(left is preview, right is latest)
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| // async reset | ||
| // increment address when enabled | ||
| always @(posedge clk or posedge rst) | ||
| if (rst) | ||
| addr <= 0; | ||
| else if (en) begin | ||
| if (addr == MAX_DATA-1) | ||
| if ({'0, addr} == MAX_DATA-1) |
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I would not include this change, it's fine to get some linting messages from verilator IMO (gives people some idea of what to expect from verilator too).
README.md
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does not perform any syntax checking
Is an exaggeration. Maybe: "does not perform robust syntax checking"?
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I see it more as a statement of intent. read_verilog doesn't try to check if the input is correct or not, it just proceeds assuming it is correct. If that turns out to be a wrong assumption it will sometimes error out, but often not in a way that is particularly useful for the user for finding the problem. Sometimes it will also just continue, and end up with who knows what netlist. Given the history of this code and the alternatives, we think it would be a waste of effort to change that.
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What are the reasons/motivation for this change?
Users are often confused and/or surprised when the
read_verilogfrontend runs into syntactical edge cases that it doesn't handle well.Explain how this is achieved.
Mention Verilator (and
verilator --lint-only) in a few places and reiterate thatread_verilogdoes not lint, and you should lint your code before trying to use it.If applicable, please suggest to reviewers how they can test the change.
Preview available on readthedocs. Note that preview builds show todos, which are normally hidden.