sstc: STIP and VSTIP of mip reverts behavior if xenvcfg.STCE=0

When menvcfg.STCE=0, mip.STIP reverts to its defined behavior as if
unsupporting Sstc extension. When henvcfg.STCE=0, mip.VSTIP reverts
to its defined behavior as if unsupporting Sstc extension. [riscvarchive/riscv-time-compare#5]

The previous Sstc implementation does not respect the xenvcfg.STCE.
In other words, the Sstc may assert mip.STIP (mip.VSTIP) when
menvcfg.STCE=0 (henvcfg.STCE=0), which is a misbehaving.

This commit presents a proposal that respects the xenvcf.STCE by
utilizing the write mask of mip_csr_t::backdoor_write_with_mask()
function. If menvcfg.STCE=0 (henvcfg.STCE=0), the corresponding
bit of mip.STIP (mip.VSTIP) in the write mask should be 0 to revert
the behavior as if unsupporting Sstec extension.

riscv/csrs.cc

@@ -1075,7 +1075,8 @@ void time_counter_csr_t::sync(const reg_t val) noexcept {
  if (proc->extension_enabled(EXT_SSTC)) {
  const reg_t mip_val = (shadow_val >= state->stimecmp->read() ? MIP_STIP : 0) |
  (shadow_val + state->htimedelta->read() >= state->vstimecmp->read() ? MIP_VSTIP : 0);
- state->mip->backdoor_write_with_mask(MIP_STIP | MIP_VSTIP, mip_val);
+ const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0);
+ state->mip->backdoor_write_with_mask(mask, mip_val);
  }
 }
 
@@ -1533,7 +1534,8 @@ stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const
 }
 
 bool stimecmp_csr_t::unlogged_write(const reg_t val) noexcept {
- state->mip->backdoor_write_with_mask(intr_mask, state->time->read() >= val ? intr_mask : 0);
+ const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0);
+ state->mip->backdoor_write_with_mask(mask, state->time->read() >= val ? intr_mask : 0);
  return basic_csr_t::unlogged_write(val);
 }