Merge pull request #26 from UMN-CMS/NewTXRX

New TXRX mapping to Engine Elinks
UMN-CMS · Oct 21, 2024 · e62357a · e62357a
2 parents bd35572 + cb5b3f5
commit e62357a
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Showing 5 changed files with 39 additions and 33 deletions.
diff --git a/run_bert.py b/run_bert.py
@@ -31,7 +31,8 @@ class BERT(Test):
     def __init__(self, conn, board_sn=-1, tester='', module=None, clock=True):
         self.info_dict = {'name': "Bit Error Rate Test", 'board_sn': board_sn, 'tester': tester}
         self.conn = conn
-        Test.__init__(self, self.bert, self.info_dict, conn, output='/home/HGCAL_pro/BERT.csv', iskip=5, nbits=1e8, module=module, clock=clock)
+        self.output = Path(__file__).parent / "BERT.csv"
+        Test.__init__(self, self.bert, self.info_dict, conn, output=self.output, iskip=5, nbits=1e8, module=module, clock=clock)
 
     def bert(self, **kwargs):
         self.scans = []
@@ -63,7 +64,7 @@ def bert(self, **kwargs):
         """
 
         self.conn.send("LCD ; Percent:{:3f} Test:4".format(0.5))
-        fitdata = FitData("/home/HGCAL_pro/BERT.csv", self.conn, scan_mask=self.scan_mask, iskip=self.iskip)
+        fitdata = FitData(self.output, self.conn, scan_mask=self.scan_mask, iskip=self.iskip)
 
         results = fitdata.get_results()
         self.passed = True
@@ -164,9 +165,9 @@ def get_links(self, board_sn="3205WEDBG100001", cfg_path = Path(__file__).parent
         if module is not None:
 
             inputs = self.wag_info["Mod{}".format(module)]["Inputs"]
-            print(inputs)
+            print("Inputs", inputs)
             outputs = self.wag_info["Mod{}".format(module)]["Outputs"]
-            print(outputs)
+            print("Outputs", outputs)
 
             nin = len(inputs.keys())
             nout = len(outputs.keys())
@@ -190,11 +191,14 @@ def get_links(self, board_sn="3205WEDBG100001", cfg_path = Path(__file__).parent
 
                 new_in_dict = {}
                 for key,i in in_dict.items():
-                    if "XING" not in i["Eng_Elink"] and "TRIG4" not in i["Eng_Elink"]:
+                    if "XING" not in i["Eng_Elink"] and "TRIG4" not in i["Mod_Elink"]:
                         new_in_dict[key] = i
 
                 out_dict = self.wag_info["Mod{}".format(mod)]["Outputs"]
 
+                print(new_in_dict)
+                print(out_dict)
+
                 nin = len(new_in_dict.keys())
                 nout = len(out_dict.keys())
                 print("Module {} has {} inputs and {} outputs".format(mod, nin, nout))
@@ -251,15 +255,15 @@ def get_links(self, board_sn="3205WEDBG100001", cfg_path = Path(__file__).parent
 
             else:
                 scan_mask[8] = 1
-                link_names[8] = "CLK0"
+                link_names[8] = "CLK1"
 
                 if self.wag_info["NumMod"] >= 2:
                     scan_mask[9] = 2
-                    link_names[9] = "CLK1"
+                    link_names[9] = "CLK2"
 
                 if self.wag_info["NumMod"] == 3:
                     scan_mask[10] = 3
-                    link_names[10] = "CLK2"
+                    link_names[10] = "CLK3"
 
         link_file.close()
         print(scan_mask)

diff --git a/run_tests.py b/run_tests.py
@@ -15,15 +15,15 @@
 def run_tests(test_info):
 
     module = None
-    print("Running ADC Self Test")
-    ADC(c1, **test_info)
-    print("Running General Resistance")
-    gen_resist_test(c1, module = module, **test_info)
-    print("Running ID Resistance Check")
-    id_resist_test(c1, **test_info)
-    print("Running IIC Check")
-    IIC_Check(c1, module = module, **test_info)
-    print("Running BERT")
+    #print("Running ADC Self Test")
+    #ADC(c1, **test_info)
+    #print("Running General Resistance")
+    #gen_resist_test(c1, module = module, **test_info)
+    #print("Running ID Resistance Check")
+    #id_resist_test(c1, **test_info)
+    #print("Running IIC Check")
+    #IIC_Check(c1, module = module, **test_info)
+    #print("Running BERT")
     BERT(c1, module = module, clock=True, **test_info) 
 
 #sn = sys.argv[1]

diff --git a/static/txrx.json b/static/txrx.json
@@ -1,23 +1,25 @@
 {
     "__description__": "This file is used to determine which TXs and RXs correspond to a given wagon elink. This is dependent on firmware version and may need to be updated if the firmware is updated.",
     "TX": [
-        {"num": 0, "link": "CLK"},
-        {"num": 1, "link": "DAQ0"},
-        {"num": 2, "link": "DAQ1"},
-        {"num": 3, "link": ""},
-        {"num": 4, "link": ""}
+        {"num": 0, "link": "CLK1"},
+        {"num": 1, "link": "CLK2"},
+        {"num": 2, "link": "CLK3"},
+        {"num": 4, "link": "DAQ0"},
+        {"num": 5, "link": "DAQ1"},
+        {"num": 6, "link": "DAQ2"},
+        {"num": 7, "link": "X_DAQ"}
     ],
     "RX": [
-        {"num": 0, "link": "TRIG0"},
-        {"num": 1, "link": "TRIG1"},
-        {"num": 2, "link": "TRIG2"},
+        {"num": 0, "link": "TRIG6"},
+        {"num": 1, "link": "TRIG5"},
+        {"num": 2, "link": "TRIG4"},
         {"num": 3, "link": "TRIG3"},
-        {"num": 4, "link": "TRIG4"},
-        {"num": 5, "link": "TRIG5"},
-        {"num": 6, "link": "TRIG6"},
-        {"num": 7, "link": "CTL0"},
-        {"num": 8, "link": "CTL1"},
-        {"num": 9, "link": ""},
+        {"num": 4, "link": "TRIG2"},
+        {"num": 5, "link": "TRIG1"},
+        {"num": 6, "link": "TRIG0"},
+        {"num": 7, "link": "CTL1"},
+        {"num": 8, "link": "CTL2"},
+        {"num": 9, "link": "CTL3"},
         {"num": 10, "link": ""},
         {"num": 11, "link": ""},
         {"num": 12, "link": ""}

diff --git a/static/wagonConfig.json b/static/wagonConfig.json
@@ -2865,4 +2865,4 @@
             }
         }
     }
-}
+}
diff --git a/wagoneer.py b/wagoneer.py
@@ -350,7 +350,7 @@ def cleanup(val):
         wagoneer.do_ber(True)
 
     if args.scan:
-        wagoneer.scan(1)
+        wagoneer.scan(10)
 
     if args.prbslen > 0:
         wagoneer.set_prbs_len(args.prbslen)
-Original file line number
+Diff line change
@@ Expand Up / @@ -2865,4 +2865,4 @@ @@
                 }
             }
         }
-    }
+    }