feat: generate gl includes for user projects

This enables running GL tests on the final GL netlist of the actual chip

project.py

@@ -67,9 +67,12 @@ def load_metrics(self):
  except FileNotFoundError:
  self.metrics = {}
 
+ def is_chip_rom(self):
+ return self.get_macro_name() == "tt_um_chip_rom"
+
  def check_ports(self):
  top = self.get_macro_name()
- if not self.is_user_project and top == "tt_um_chip_rom":
+ if not self.is_user_project and self.is_chip_rom():
  return # Chip ROM is auto generated, so we don't have the verilog yet
  sources = [os.path.join(self.src_dir, src) for src in self.src_files]
  source_list = " ".join(sources)

shuttle.py

@@ -93,6 +93,14 @@ def configure_mux(self):
  with open("shuttle_index.json", "w") as shuttle_index_file:
  json.dump(shuttle_index_data, shuttle_index_file, indent=2)
 
+ with open("verilog/includes/includes.gl.user_projects", "w") as includes_file:
+ for project in self.projects:
+ if project.is_chip_rom():
+ continue
+ includes_file.write(
+ f"$(USER_PROJECT_VERILOG)/../projects/{project.top_module}/{project.top_module}.v\n"
+ )
+
  def list(self):
  for project in self.projects:
  logging.info(project)