feat(fpga): read seed / target frequency from environment

Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
TinyTapeout · May 1, 2024 · 0c171af · 0c171af
1 parent b6ec741
commit 0c171af
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/project.py b/project.py
@@ -530,7 +530,10 @@ def create_fpga_bitstream(self):
  logging.error("synthesis failed")
  exit(1)
 
- nextpnr_cmd = f"nextpnr-ice40 -l {build_dir}/02-nextpnr.log --pcf-allow-unconstrained --seed 10 --freq 48 --package sg48 --up5k --asc {build_dir}/tt_fpga.asc --pcf {SCRIPT_DIR}/fpga/tt_fpga_top.pcf --json {build_dir}/tt_fpga.json"
+ seed = os.getenv("TT_FPGA_SEED", "10")
+ freq = os.getenv("TT_FPGA_FREQ", "12")
+
+ nextpnr_cmd = f"nextpnr-ice40 -l {build_dir}/02-nextpnr.log --pcf-allow-unconstrained --seed {seed} --freq {freq} --package sg48 --up5k --asc {build_dir}/tt_fpga.asc --pcf {SCRIPT_DIR}/fpga/tt_fpga_top.pcf --json {build_dir}/tt_fpga.json"
  logging.debug(nextpnr_cmd)
  p = subprocess.run(nextpnr_cmd, shell=True)
  if p.returncode != 0: