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{ | ||
"app": "Tiny Tapeout tt09 a48b1c74", | ||
"repo": "https://github.com/mikegoelzer/tinytapeoutverilog2024", | ||
"commit": "5d90b3688d0deda9285a3dd7f5b6af58ae06f2ea", | ||
"workflow_url": "https://github.com/mikegoelzer/tinytapeoutverilog2024/actions/runs/11735509474", | ||
"sort_id": 1731066792080, | ||
"openlane_version": "OpenLane2 2.1.9", | ||
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" | ||
} |
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<!--- | ||
This file is used to generate your project datasheet. Please fill in the information below and delete any unused | ||
sections. | ||
You can also include images in this folder and reference them in the markdown. Each image must be less than | ||
512 kb in size, and the combined size of all images must be less than 1 MB. | ||
--> | ||
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## How it works | ||
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A two digit 7-segment display shows a hex representation of the 8-bit value provided on `ui[7:0]`. Byte `ui[7:0]` is latched when the write enable signal on `uio[0]` is high at a rising clock edge. The display is driven continuously by `uo[6:0]` with `uo[7]` controlling which digit is being driven (0=left digit, 1=right digit). | ||
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## How to test | ||
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Connect the 7-segment display to the `uo[6:0]` outputs (segment 'a' is `uo[0]`, ..., segment 'g' is `uo[6]`). Connect the `uo[7]` signal to a switch to control which digit is being driven. | ||
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Connect wires to the `ui[7:0]` and `uio[0]` inputs. Ground all of `ui[7:0]` and set `uio[0]` low and verify that the display is `00`. Pull `ui[0]` high and briefly pull `uio[0]` high and the display value should change to `01`. | ||
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Pull `ui[0]` low again and displayed value should not change; now also pull `uio[0]` high and the display should return to `00`. | ||
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## External hardware | ||
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Use this [two digit 7-segment display](https://github.com/mikegoelzer/7seg-2digit/) (or [this one](https://digilent.com/shop/pmod-ssd-seven-segment-display/)) to test the project. |
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# Tiny Tapeout project information | ||
project: | ||
title: "7-Segment Byte Display" | ||
author: "Mike Goelzer" | ||
discord: "owngoal" | ||
description: "Drives a single hex digit 7-segment display based on the value of a 1-byte input" | ||
language: "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc | ||
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) | ||
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# How many tiles your design occupies? A single tile is about 167x108 uM. | ||
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 | ||
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# Your top module name must start with "tt_um_". Make it unique by including your github username: | ||
top_module: "tt_um_mikegoelzer_7segmentbyte" | ||
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# List your project's source files here. | ||
# Source files must be in ./src and you must list each source file separately, one per line. | ||
# Don't forget to also update `PROJECT_SOURCES` in test/Makefile. | ||
source_files: | ||
- "project.v" | ||
- "7seg.sv" | ||
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. | ||
pinout: | ||
# Inputs | ||
ui[0]: "Byte to display on 7-segment display (rightmost / low order bit)" | ||
ui[1]: "Byte to display on 7-segment display (next bit)" | ||
ui[2]: "Byte to display on 7-segment display (next bit)" | ||
ui[3]: "Byte to display on 7-segment display (next bit)" | ||
ui[4]: "Byte to display on 7-segment display (next bit)" | ||
ui[5]: "Byte to display on 7-segment display (next bit)" | ||
ui[6]: "Byte to display on 7-segment display (next bit)" | ||
ui[7]: "Byte to display on 7-segment display (leftmost / high order bit)" | ||
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# Outputs | ||
uo[0]: "7-segment display a" | ||
uo[1]: "7-segment display b" | ||
uo[2]: "7-segment display c" | ||
uo[3]: "7-segment display d" | ||
uo[4]: "7-segment display e" | ||
uo[5]: "7-segment display f" | ||
uo[6]: "7-segment display g" | ||
uo[7]: "(unused)" | ||
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# Bidirectional pins | ||
uio[0]: "write enable (1=latch byte value on ui[7:0] and display it, 0=ignore ui[7:0] and keep displaying the current value)" | ||
uio[1]: "(unused)" | ||
uio[2]: "(unused)" | ||
uio[3]: "(unused)" | ||
uio[4]: "(unused)" | ||
uio[5]: "(unused)" | ||
uio[6]: "(unused)" | ||
uio[7]: "(unused)" | ||
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# Do not change! | ||
yaml_version: 6 |
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