docs(datasheet): add chip map and GDS renders #57
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| name: formal | |
| on: | |
| workflow_dispatch: | |
| push: | |
| # Don't run on project submissions: | |
| branches-ignore: | |
| - projects/tt_um_* | |
| pull_request: | |
| # Don't run on project submissions: | |
| paths-ignore: | |
| - projects/tt_um_*/** | |
| jobs: | |
| formal: | |
| runs-on: ubuntu-24.04 | |
| steps: | |
| - name: checkout repo | |
| uses: actions/checkout@v4 | |
| with: | |
| submodules: recursive | |
| - name: Set up python | |
| uses: actions/setup-python@v5 | |
| with: | |
| python-version: '3.11' | |
| cache: 'pip' | |
| - name: install oss-cad-suite (cocotb / iverilog) | |
| uses: YosysHQ/setup-oss-cad-suite@v3 | |
| with: | |
| github-token: ${{ secrets.GITHUB_TOKEN }} | |
| - run: | | |
| yosys --version | |
| - name: Python requirements | |
| run: pip3 install -r tt-multiplexer/py/requirements.txt | |
| - name: formal tristate | |
| working-directory: tt-multiplexer | |
| run: make formal_tristate | |
| - name: formal tristate | |
| working-directory: tt-multiplexer | |
| run: make formal_connectivity |