Update project tt_um_alexsegura_pong (alex-segura/tt06-pong)

projects/tt_um_alexsegura_pong/LICENSE

@@ -0,0 +1,201 @@
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projects/tt_um_alexsegura_pong/commit_id.json

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+{
+  "app": "Tiny Tapeout tt06 e8c5040d",
+  "repo": "https://github.com/alex-segura/tt06-pong",
+  "commit": "dab9f8b3fb9bbaca501e21cef5d3dcb33f9b22a5",
+  "workflow_url": "https://github.com/alex-segura/tt06-pong/actions/runs/7875283322",
+  "sort_id": 1707757950612,
+  "openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
+  "pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"
+}

projects/tt_um_alexsegura_pong/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+![screenshot](screen.png)
+
+## How it works
+
+The pixel clock drives a VGA sync generator that scans the screen. Logic in `pong.v` determines whether to draw a pixel.
+
+At each vsync, collisions are detected and the state of the game is updated.
+
+For the paddle controls, the game uses modified versions of the debounce and encoder logic from the course to generate the control signals.
+
+## How to test
+
+Two vertical paddles and a ball should render at 640x480 resolution. A vertical "net" should be visible at the middle of the screen. Paddles should respond to the encoders. The ball should bounce from the top and bottom boundaries of the screen and should bounce off the paddles. The game should reset when the ball crosses beyond either paddle.
+
+The verilog code can be run under verilator simulation:
+
+```shell
+cd src
+make -B pong
+./obj_dir/pong
+```
+
+SDL2 is a necessary dependency.
+
+W and S control the left paddle. Up and down arrow keys control the right paddle.
+
+## External hardware
+
+- Two rotary encoders, one for each paddle.
+- [TinyVGA](https://github.com/mole99/tiny-vga) Pmod or similar.

projects/tt_um_alexsegura_pong/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "Pong"                    # Project title
+  author:       "Alex Segura"             # Your name
+  discord:      "tridearm"                # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "2-player pong game"      # One line description of what your project does
+  language:     "Verilog"                 # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     25175000                  # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_alexsegura_pong"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:
+    - "tt_um_alexsegura_pong.v"
+    - "pong.v"
+    - "encoder.v"
+    - "debounce.v"
+    - "paddle.v"
+    - "hvsync_generator.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: "Paddle 1 encoder A"
+  ui[1]: "Paddle 1 encoder B"
+  ui[2]: "Paddle 2 encoder A"
+  ui[3]: "Paddle 2 encoder B"
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
+
+  # Outputs
+  uo[0]: "R0"
+  uo[1]: "G0"
+  uo[2]: "B0"
+  uo[3]: "VSYNC"
+  uo[4]: "R1"
+  uo[5]: "G1"
+  uo[6]: "B1"
+  uo[7]: "HSYNC"
+
+  # Bidirectional pins
+  uio[0]: ""
+  uio[1]: ""
+  uio[2]: ""
+  uio[3]: ""
+  uio[4]: ""
+  uio[5]: ""
+  uio[6]: ""
+  uio[7]: ""
+
+# Do not change!
+yaml_version: 6

projects/tt_um_alexsegura_pong/stats/metrics.csv

@@ -0,0 +1,2 @@
+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_alexsegura_pong,wokwi,flow completed,0h2m27s0ms,0h2m3s0ms,106935.66928362013,0.01795472,53467.83464181006,55.11,78.37960000000001,555.88,867,0,0,0,0,0,0,0,0,0,0,-1,-1,19836,6453,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,13053322.0,0.0,42.88,30.92,6.34,0.86,-1,1247,1556,84,359,0,0,0,1307,41,0,56,118,184,197,28,25,120,118,15,755,225,0,372,960,2312,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_alexsegura_pong/stats/synthesis-stats.txt

@@ -0,0 +1,74 @@
+
+67. Printing statistics.
+
+=== tt_um_alexsegura_pong ===
+
+   Number of wires:                851
+   Number of wire bits:            886
+   Number of public wires:         126
+   Number of public wire bits:     161
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                867
+     sky130_fd_sc_hd__a2111o_2       2
+     sky130_fd_sc_hd__a211o_2        3
+     sky130_fd_sc_hd__a211oi_2       1
+     sky130_fd_sc_hd__a21bo_2        8
+     sky130_fd_sc_hd__a21o_2        18
+     sky130_fd_sc_hd__a21oi_2       31
+     sky130_fd_sc_hd__a221o_2       16
+     sky130_fd_sc_hd__a221oi_2       1
+     sky130_fd_sc_hd__a22o_2        13
+     sky130_fd_sc_hd__a22oi_2        1
+     sky130_fd_sc_hd__a2bb2o_2       2
+     sky130_fd_sc_hd__a31o_2        12
+     sky130_fd_sc_hd__a31oi_2        1
+     sky130_fd_sc_hd__a32o_2         6
+     sky130_fd_sc_hd__a41o_2         4
+     sky130_fd_sc_hd__and2_2        60
+     sky130_fd_sc_hd__and2b_2       30
+     sky130_fd_sc_hd__and3_2        31
+     sky130_fd_sc_hd__and3b_2        4
+     sky130_fd_sc_hd__and4_2         8
+     sky130_fd_sc_hd__and4b_2        1
+     sky130_fd_sc_hd__and4bb_2       1
+     sky130_fd_sc_hd__buf_1         83
+     sky130_fd_sc_hd__buf_2          8
+     sky130_fd_sc_hd__conb_1        16
+     sky130_fd_sc_hd__dfxtp_2      115
+     sky130_fd_sc_hd__inv_2         24
+     sky130_fd_sc_hd__mux2_2        17
+     sky130_fd_sc_hd__nand2_2       53
+     sky130_fd_sc_hd__nand3_2        3
+     sky130_fd_sc_hd__nand3b_2       2
+     sky130_fd_sc_hd__nand4_2        1
+     sky130_fd_sc_hd__nor2_2        40
+     sky130_fd_sc_hd__nor3_2         3
+     sky130_fd_sc_hd__nor4_2         1
+     sky130_fd_sc_hd__o2111a_2       1
+     sky130_fd_sc_hd__o211a_2       16
+     sky130_fd_sc_hd__o21a_2         9
+     sky130_fd_sc_hd__o21ai_2       28
+     sky130_fd_sc_hd__o21ba_2        2
+     sky130_fd_sc_hd__o21bai_2       1
+     sky130_fd_sc_hd__o221a_2        4
+     sky130_fd_sc_hd__o221ai_2       1
+     sky130_fd_sc_hd__o22a_2         7
+     sky130_fd_sc_hd__o2bb2a_2       3
+     sky130_fd_sc_hd__o311a_2        1
+     sky130_fd_sc_hd__o31a_2         2
+     sky130_fd_sc_hd__o32a_2         1
+     sky130_fd_sc_hd__o41a_2         4
+     sky130_fd_sc_hd__or2_2         38
+     sky130_fd_sc_hd__or2b_2        18
+     sky130_fd_sc_hd__or3_2          6
+     sky130_fd_sc_hd__or3b_2         5
+     sky130_fd_sc_hd__or4_2         18
+     sky130_fd_sc_hd__or4b_2        11
+     sky130_fd_sc_hd__or4bb_2        1
+     sky130_fd_sc_hd__xnor2_2       46
+     sky130_fd_sc_hd__xor2_2        24
+
+   Chip area for module '\tt_um_alexsegura_pong': 8773.414400
+