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update sta #255

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merged 6 commits into from
Jan 2, 2025
Merged

update sta #255

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26fccd8
report_checks -fileds hierarchical_pins resolves #136
jjcherry56 Dec 26, 2024
adaf73c
verilog reader cleanups
jjcherry56 Dec 28, 2024
5824e44
set_report_path_field_properties error->warn
jjcherry56 Dec 29, 2024
b0bd2d8
power doc
jjcherry56 Dec 31, 2024
a139d6b
get_* do not require liberty resolves #161
jjcherry56 Dec 31, 2024
33b7b5b
Merge branch 'master' of https://github.com/parallaxsw/OpenSTA into u…
eder-matheus Jan 1, 2025
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3 changes: 3 additions & 0 deletions doc/ChangeLog.txt
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Expand Up @@ -33,6 +33,9 @@ is now supported by the the read_saif command.
The report_checks -group_count option has been renamed to -group_path_count.
The report_checks -endpoing_count option has been renamed to -endpoint_path_count.

The report_checks -field hierarchical_pins field reports hierarical pins between
a driver and a load in the path report.

Release 2.5.0 2024/01/17
-------------------------

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4 changes: 2 additions & 2 deletions graph/Graph.i
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Expand Up @@ -413,8 +413,8 @@ latch_d_to_q_en()
{
if (self->role() == TimingRole::latchDtoQ()) {
Sta *sta = Sta::sta();
const Network *network = sta->ensureLinked();
const Graph *graph = sta->graph();
const Network *network = sta->network();
const Graph *graph = sta->ensureGraph();
Pin *from_pin = self->from(graph)->pin();
Instance *inst = network->instance(from_pin);
LibertyCell *lib_cell = network->libertyCell(inst);
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6 changes: 5 additions & 1 deletion include/sta/Sta.hh
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Expand Up @@ -112,6 +112,7 @@ public:
bool infer_latches);
bool setMinLibrary(const char *min_filename,
const char *max_filename);
bool readVerilog(const char *filename);
// Network readers call this to notify the Sta to delete any previously
// linked network.
void readNetlistBefore();
Expand Down Expand Up @@ -889,6 +890,7 @@ public:
void setReportPathFormat(ReportPathFormat format);
void setReportPathFieldOrder(StringSeq *field_names);
void setReportPathFields(bool report_input_pin,
bool report_hier_pins,
bool report_net,
bool report_cap,
bool report_slew,
Expand Down Expand Up @@ -1230,8 +1232,10 @@ public:

void setTclInterp(Tcl_Interp *interp);
Tcl_Interp *tclInterp();
// Ensure a network has been read, linked and liberty libraries exist.
// Ensure a network has been read, and linked.
Network *ensureLinked();
// Ensure a network has been read, linked and liberty libraries exist.
Network *ensureLibLinked();
void ensureLevelized();
// Ensure that the timing graph has been built.
Graph *ensureGraph();
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32 changes: 19 additions & 13 deletions network/Network.i
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Expand Up @@ -618,13 +618,16 @@ void finish() { delete self; }
} // LibraryIterator methods

%extend Cell {
const char *name() { return Sta::sta()->ensureLinked()->name(self); }
Library *library() { return Sta::sta()->ensureLinked()->library(self); }
LibertyCell *liberty_cell() { return Sta::sta()->ensureLinked()->libertyCell(self); }
bool is_leaf() { return Sta::sta()->ensureLinked()->isLeaf(self); }
const char *name() { return Sta::sta()->cmdNetwork()->name(self); }
Library *library() { return Sta::sta()->cmdNetwork()->library(self); }
LibertyCell *liberty_cell() { return Sta::sta()->cmdNetwork()->libertyCell(self); }
bool is_leaf() { return Sta::sta()->cmdNetwork()->isLeaf(self); }
CellPortIterator *
port_iterator() { return Sta::sta()->ensureLinked()->portIterator(self); }
string get_attribute(const char *key) { return Sta::sta()->ensureLinked()->getAttribute(self, key); }
port_iterator() { return Sta::sta()->cmdNetwork()->portIterator(self); }
string get_attribute(const char *key)
{
return Sta::sta()->cmdNetwork()->getAttribute(self, key);
}

Port *
find_port(const char *name)
Expand Down Expand Up @@ -654,7 +657,7 @@ void finish() { delete self; }
%extend Port {
const char *bus_name() { return Sta::sta()->ensureLinked()->busName(self); }
Cell *cell() { return Sta::sta()->ensureLinked()->cell(self); }
LibertyPort *liberty_port() { return Sta::sta()->ensureLinked()->libertyPort(self); }
LibertyPort *liberty_port() { return Sta::sta()->ensureLibLinked()->libertyPort(self); }
bool is_bus() { return Sta::sta()->ensureLinked()->isBus(self); }
PortMemberIterator *
member_iterator() { return Sta::sta()->ensureLinked()->memberIterator(self); }
Expand All @@ -670,7 +673,7 @@ void finish() { delete self; }
%extend Instance {
Instance *parent() { return Sta::sta()->ensureLinked()->parent(self); }
Cell *cell() { return Sta::sta()->ensureLinked()->cell(self); }
LibertyCell *liberty_cell() { return Sta::sta()->ensureLinked()->libertyCell(self); }
LibertyCell *liberty_cell() { return Sta::sta()->ensureLibLinked()->libertyCell(self); }
bool is_leaf() { return Sta::sta()->ensureLinked()->isLeaf(self); }
InstanceChildIterator *
child_iterator() { return Sta::sta()->ensureLinked()->childIterator(self); }
Expand All @@ -683,7 +686,10 @@ find_pin(const char *name)
{
return Sta::sta()->ensureLinked()->findPin(self, name);
}
string get_attribute(const char *key) { return Sta::sta()->ensureLinked()->getAttribute(self, key); }
string get_attribute(const char *key) {
return Sta::sta()->ensureLinked()->getAttribute(self, key);
}

} // Instance methods

%extend InstanceChildIterator {
Expand Down Expand Up @@ -716,7 +722,7 @@ Instance *instance() { return Sta::sta()->ensureLinked()->instance(self); }
Net *net() { return Sta::sta()->ensureLinked()->net(self); }
Port *port() { return Sta::sta()->ensureLinked()->port(self); }
Term *term() { return Sta::sta()->ensureLinked()->term(self); }
LibertyPort *liberty_port() { return Sta::sta()->ensureLinked()->libertyPort(self); }
LibertyPort *liberty_port() { return Sta::sta()->ensureLibLinked()->libertyPort(self); }
bool is_driver() { return Sta::sta()->ensureLinked()->isDriver(self); }
bool is_load() { return Sta::sta()->ensureLinked()->isLoad(self); }
bool is_leaf() { return Sta::sta()->ensureLinked()->isLeaf(self); }
Expand Down Expand Up @@ -768,7 +774,7 @@ capacitance(Corner *corner,
const MinMax *min_max)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
float pin_cap, wire_cap;
sta->connectedCap(self, corner, min_max, pin_cap, wire_cap);
return pin_cap + wire_cap;
Expand All @@ -779,7 +785,7 @@ pin_capacitance(Corner *corner,
const MinMax *min_max)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
float pin_cap, wire_cap;
sta->connectedCap(self, corner, min_max, pin_cap, wire_cap);
return pin_cap;
Expand All @@ -790,7 +796,7 @@ wire_capacitance(Corner *corner,
const MinMax *min_max)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
float pin_cap, wire_cap;
sta->connectedCap(self, corner, min_max, pin_cap, wire_cap);
return wire_cap;
Expand Down
17 changes: 10 additions & 7 deletions power/Power.cc
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Expand Up @@ -600,13 +600,16 @@ Power::evalBddActivity(DdNode *bdd,
Cudd_RecursiveDeref(bdd_.cuddMgr(), diff);
float var_act = var_activity.activity() * diff_duty;
activity += var_act;
const Clock *clk = findClk(pin);
float clk_period = clk ? clk->period() : 1.0;
debugPrint(debug_, "power_activity", 3, "var %s %.3e * %.3f = %.3e",
port->name(),
var_activity.activity() / clk_period,
diff_duty,
var_act / clk_period);
if (debug_->check("power_activity", 3)) {
const Clock *clk = findClk(pin);
float clk_period = clk ? clk->period() : 1.0;
debugPrint(debug_, "power_activity", 3, "var %s%s %.3e * %.3f = %.3e",
port->name(),
clk ? "" : " (unclocked)",
var_activity.activity() / clk_period,
diff_duty,
var_act / clk_period);
}
}
}
return activity;
Expand Down
4 changes: 2 additions & 2 deletions power/Power.i
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Expand Up @@ -109,7 +109,7 @@ read_vcd_file(const char *filename,
const char *scope)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
readVcdActivities(filename, scope, sta);
}

Expand All @@ -136,7 +136,7 @@ read_saif_file(const char *filename,
const char *scope)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
return readSaif(filename, scope, sta);
}

Expand Down
1 change: 1 addition & 0 deletions power/Power.tcl
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Expand Up @@ -271,6 +271,7 @@ proc set_power_activity { args } {

################################################################

# Deprecated 9/2024
define_cmd_args "read_power_activities" { [-scope scope] -vcd filename }

proc read_power_activities { args } {
Expand Down
1 change: 1 addition & 0 deletions power/SaifReader.cc
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Expand Up @@ -89,6 +89,7 @@ SaifReader::read()
// yyparse returns 0 on success.
bool success = (::SaifParse_parse() == 0);
gzclose(stream_);
report_->reportLine("Annotated %zu pin activities.", annotated_pins_.size());
return success;
}
else
Expand Down
8 changes: 4 additions & 4 deletions sdf/Sdf.i
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Expand Up @@ -51,7 +51,7 @@ read_sdf_file(const char *filename,
MinMaxAllNull *cond_use)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
sta->ensureGraph();
if (stringEq(path, ""))
path = NULL;
Expand All @@ -72,7 +72,7 @@ report_annotated_delay_cmd(bool report_cells,
bool report_constant_arcs)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
sta->ensureGraph();
reportAnnotatedDelay(report_cells, report_nets,
report_in_ports, report_out_ports,
Expand All @@ -95,7 +95,7 @@ report_annotated_check_cmd(bool report_setup,
bool report_constant_arcs)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
sta->ensureGraph();
reportAnnotatedCheck(report_setup, report_hold,
report_recovery, report_removal,
Expand All @@ -116,7 +116,7 @@ write_sdf_cmd(char *filename,
bool no_version)
{
Sta *sta = Sta::sta();
sta->ensureLinked();
sta->ensureLibLinked();
sta->writeSdf(filename, corner, divider, include_typ, digits, gzip,
no_timestamp, no_version);
}
Expand Down
34 changes: 17 additions & 17 deletions search/Property.cc
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Expand Up @@ -680,7 +680,7 @@ getProperty(const Library *lib,
const char *property,
Sta *sta)
{
Network *network = sta->ensureLinked();
Network *network = sta->cmdNetwork();
if (stringEqual(property, "name")
|| stringEqual(property, "full_name"))
return PropertyValue(network->name(lib));
Expand Down Expand Up @@ -711,8 +711,8 @@ getProperty(const LibertyCell *cell,
|| stringEqual(property, "base_name"))
return PropertyValue(cell->name());
else if (stringEqual(property, "full_name")) {
Network *network = sta->ensureLinked();
auto lib = cell->libertyLibrary();
Network *network = sta->cmdNetwork();
LibertyLibrary *lib = cell->libertyLibrary();
string lib_name = lib->name();
string cell_name = cell->name();
string full_name = lib_name + network->pathDivider() + cell_name;
Expand Down Expand Up @@ -741,7 +741,7 @@ getProperty(const Cell *cell,
const char *property,
Sta *sta)
{
Network *network = sta->ensureLinked();
Network *network = sta->cmdNetwork();
if (stringEqual(property, "name")
|| stringEqual(property, "base_name"))
return PropertyValue(network->name(cell));
Expand All @@ -767,7 +767,7 @@ getProperty(const Port *port,
const char *property,
Sta *sta)
{
Network *network = sta->ensureLinked();
Network *network = sta->cmdNetwork();
if (stringEqual(property, "name")
|| stringEqual(property, "full_name"))
return PropertyValue(network->name(port));
Expand Down Expand Up @@ -819,7 +819,7 @@ portSlewProperty(const Port *port,
const MinMax *min_max,
Sta *sta)
{
Network *network = sta->ensureLinked();
Network *network = sta->ensureLibLinked();
Instance *top_inst = network->topInstance();
Pin *pin = network->findPin(top_inst, port);
return pinSlewProperty(pin, min_max, sta);
Expand All @@ -831,7 +831,7 @@ portSlewProperty(const Port *port,
const MinMax *min_max,
Sta *sta)
{
Network *network = sta->ensureLinked();
Network *network = sta->ensureLibLinked();
Instance *top_inst = network->topInstance();
Pin *pin = network->findPin(top_inst, port);
return pinSlewProperty(pin, rf, min_max, sta);
Expand All @@ -842,7 +842,7 @@ portSlackProperty(const Port *port,
const MinMax *min_max,
Sta *sta)
{
Network *network = sta->ensureLinked();
Network *network = sta->ensureLibLinked();
Instance *top_inst = network->topInstance();
Pin *pin = network->findPin(top_inst, port);
return pinSlackProperty(pin, min_max, sta);
Expand All @@ -854,7 +854,7 @@ portSlackProperty(const Port *port,
const MinMax *min_max,
Sta *sta)
{
Network *network = sta->ensureLinked();
Network *network = sta->ensureLibLinked();
Instance *top_inst = network->topInstance();
Pin *pin = network->findPin(top_inst, port);
return pinSlackProperty(pin, rf, min_max, sta);
Expand Down Expand Up @@ -1075,7 +1075,7 @@ pinSlewProperty(const Pin *pin,
const MinMax *min_max,
Sta *sta)
{
auto graph = sta->ensureGraph();
Graph *graph = sta->ensureGraph();
Vertex *vertex, *bidirect_drvr_vertex;
graph->pinVertices(pin, vertex, bidirect_drvr_vertex);
Slew slew = min_max->initValue();
Expand All @@ -1098,7 +1098,7 @@ pinSlewProperty(const Pin *pin,
const MinMax *min_max,
Sta *sta)
{
auto graph = sta->ensureGraph();
Graph *graph = sta->ensureGraph();
Vertex *vertex, *bidirect_drvr_vertex;
graph->pinVertices(pin, vertex, bidirect_drvr_vertex);
Slew slew = min_max->initValue();
Expand Down Expand Up @@ -1139,7 +1139,7 @@ getProperty(Edge *edge,
Sta *sta)
{
if (stringEqual(property, "full_name")) {
Network *network = sta->ensureLinked();
Network *network = sta->cmdNetwork();
Graph *graph = sta->ensureGraph();
const char *from = edge->from(graph)->name(network);
const char *to = edge->to(graph)->name(network);
Expand Down Expand Up @@ -1177,7 +1177,7 @@ edgeDelayProperty(Edge *edge,
for (TimingArc *arc : arc_set->arcs()) {
RiseFall *to_rf = arc->toEdge()->asRiseFall();
if (to_rf == rf) {
for (auto corner : *sta->corners()) {
for (const Corner *corner : *sta->corners()) {
DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max);
ArcDelay arc_delay = sta->arcDelay(edge, arc, dcalc_ap);
if (!delay_exists
Expand All @@ -1204,9 +1204,9 @@ getProperty(TimingArcSet *arc_set,
if (arc_set->isWire())
return PropertyValue("wire");
else {
auto from = arc_set->from()->name();
auto to = arc_set->to()->name();
auto cell_name = arc_set->libertyCell()->name();
const char *from = arc_set->from()->name();
const char *to = arc_set->to()->name();
const char *cell_name = arc_set->libertyCell()->name();
string name;
stringPrint(name, "%s %s -> %s", cell_name, from, to);
return PropertyValue(name);
Expand Down Expand Up @@ -1264,7 +1264,7 @@ getProperty(PathEnd *end,
else if (stringEqual(property, "points")) {
PathExpanded expanded(end->path(), sta);
PathRefSeq paths;
for (auto i = expanded.startIndex(); i < expanded.size(); i++) {
for (size_t i = expanded.startIndex(); i < expanded.size(); i++) {
const PathRef *path = expanded.path(i);
paths.push_back(*path);
}
Expand Down
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