Merge branch 'master' into bo-wun-update

_pages/current-projects.md

@@ -102,11 +102,6 @@ Extended reality (XR), which includes virtual and augmented reality, has the pot
 * * *
 
 ### Accelerator Architectures Leveraging Emerging Technologies
-#### MINOTAUR    
-**Kartik Prabhu, Jeffrey Yu**    
-Transformer neural networks achieve state-of-the-art accuracy on both vision and NLP tasks, but are challenging to run in an edge environment. Existing approaches to accelerating transformers face power, area, and battery life challenges, further complicated by the need to perform on-device training to achieve peak accuracy. MINOTAUR uses non-volatile Resistive RAM (RRAM) in order to achieve high performance and low energy inference and training of Transformer networks, and targets a 1-year lifetime on a coin cell battery.
-
-* * *
 
 #### EMBER    
 <img src="/assets/images/EMBER_V1_transparent_5x.png" width="200" align="left" style="padding-right: 30px; padding-bottom: 20px;">

_pages/group-photos.md

@@ -7,6 +7,18 @@ hide_hero: true
 
 <table style="width:100%">
   <tbody>
+    <tr>
+      <td style="width:50%"><img src="/assets/images/group_photo_oct_8_2023.jpg" width="800" align="center" style="padding-right: 30px; padding-bottom: 20px;"></td>
+      <td>Group photo from Alpine Inn on October 8, 2023. From left to right: Jackson Melchert, Kalhan Koul, Kathleen Feng, Kai Bartolone, Bo Wun Cheng, Jeffery Yu, Po-Han Chen, Kartik Prabhu, Michael Oduoza, Yuchen Mei, Priyanka Raina, and Calib Terrill.</td>
+    </tr>
+    <tr>
+      <td style="width:50%"><img src="/assets/images/group_photo_jun_3_2023.jpg" width="800" align="center" style="padding-right: 30px; padding-bottom: 20px;"></td>
+      <td>Group photo from Mini Golf on June 3, 2023. From left to right: Kartik Prabhu, Youngha Choi and family, Brianna McColm, Jackson Melchert, Priyanka Raina, Kathleen Feng, and Po-Han Chen.</td>
+    </tr>
+    <tr>
+      <td style="width:50%"><img src="/assets/images/group_photo_feb_18_2023.jpg" width="800" align="center" style="padding-right: 30px; padding-bottom: 20px;"></td>
+      <td>Group photo from February 18, 2023. From left to right: Po-Han Chen, Akash Levy, Yuchen Mei, Yonatan Urman, Kartik Prabhu, Jeffery Yu, Jackson Melchert, Kathleen Feng, Kalhan Koul, and Gina Sohn.</td>
+    </tr>
     <tr>
       <td style="width:50%"><img src="/assets/images/vlsi-2022.jpg" width="800" align="center" style="padding-right: 30px; padding-bottom: 20px;"></td>
       <td>Group photo from VLSI 2022 in Honolulu, HI, June 15, 2022. From left to right: Kartik Prabhu, Priyanka Raina, Kalhan Koul and Kathleen Feng.</td>

_pages/previous-students.md

@@ -16,7 +16,6 @@ hide_hero: true
 ## Undergraduate and Coterm Students
 - Akhilesh Varadan Balasingam (REU 2022)
 - Xiaoyang Ma (UGVR 2021)
-- Michael Oduoza (Academic year research in 2020 and 2021, Graduated in 2022)
 - Charles Tsao (REU 2019, REU 2020, Graduated in 2022)
 - John Kustin (REU 2020, Graduated in 2022)
 - Denisse Ventura (SURF 2020)

_pages/publications.md

@@ -6,6 +6,34 @@ hide_hero: true
 ---
 
 ## Publications    
+**Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays**    
+Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina    
+*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)*, 2024.    
+
+**MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating**    
+Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina    
+*IEEE Symposium on VLSI Technology & Circuits (VLSI)*, June 2024.    
+
+**Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications**    
+Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina    
+*IEEE Symposium on VLSI Technology & Circuits (VLSI)*, June 2024.
+
+**EMBER: Efficient Multiple-Bits-per-Cell Embedded RRAM Macro for High-Density Digital Storage**    
+Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina    
+*IEEE Journal of Solid-State Circuits (JSSC)*, 2024.    
+
+**8-bit Transformer Inference and Fine-tuning for Edge Accelerators**    
+Jeffrey Yu, Kartik Prabhu, Yonatan Urman, Robert M. Radway, Eric Han, Priyanka Raina    
+*ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)*, April 2024.    
+
+**Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays**    
+Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina    
+*Languages, Tools, and Techniques for Accelerator Design (LATTE) Workshop at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)*, April 2024.    
+
+**FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization**    
+Akash Levy, Joe Walston, Priyanka Raina, Stelios Diamantidis    
+*International Symposium on Quality Electronic Design (ISQED)*, April 2024.
+
 **PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM**    
 Anjiang Wei, Akash Levy, Pu Yi, Robert Radway, Priyanka Raina, Subhasish Mitra, Sara Achour    
 *IEEE/ACM International Conference On Computer Aided Design (ICCAD)*, October 2023.    

index.md

@@ -80,14 +80,23 @@ Stanford accelerate group works on creating high performance and energy-efficien
       </td>
     </tr>
     <tr>
-      <td style="width:18%"><img src="assets/images/pohan.jpg" width="250" align="left"></td>
+      <td style="width:18%"><img src="assets/images/bowun.jpg" width="250" align="left"></td>
       <td>
         <b>Bo-Wun Chen</b><br> 
         <b>Email:</b> bwcheng AT stanford DOT edu, <a href="https://linkedin.com/in/bo-wun-cheng/">Webpage</a><br>
         <b>About:</b> Bo-Wun Cheng is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. He received his B.S. and M.S. degrees in Computer Science from National Tsing Hua University (Taiwan) in 2021 and 2023, respectively.<br>
         <b>Research:</b> His current research interest resides in designing and architecting efficient hardware accelerators. Before joining Stanford, his research spans the fields of Graphics Processing Unit memory architecture design and computer vision.
       </td>
     </tr>
+    <tr>
+      <td style="width:18%"><img src="assets/images/michael.jpg" width="250" align="left"></td>
+      <td>
+        <b>Michael Oduoza</b><br> 
+        <b>Email:</b> mcoduoza AT stanford DOT edu, <a href="https://linkedin.com/in/michael-oduoza/">Webpage</a><br>
+        <b>About:</b> Michael Oduoza is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. He received his B.S. and M.S. degrees in Electrical Engineering from Stanford in 2021 and 2022 respectively.  <br>
+        <b>Research:</b> His research focuses on hardware/software co-design to create energy-efficient computing systems. He is broadly interested in designing new computer architectures for emerging machine learning applications. His pre-Ph.D. research spanned a range of topics, from semiconductor devices to circuits to systems.  
+      </td>
+    </tr>
   </tbody>
 </table>    
 
@@ -148,6 +157,15 @@ Stanford accelerate group works on creating high performance and energy-efficien
         <b>Research:</b> His research involves developing new applications to map onto reconfigurable logic devices (CGRAs) using the Halide language.
       </td>
     </tr>
+    <tr>
+      <td style="width:18%"><img src="/assets/images/caleb.jpg" width="250" align="left"></td>
+      <td>
+        <b>Caleb Terrill</b><br> 
+        <b>Email:</b> cterrill AT stanford DOT edu<br>
+        <b>About:</b> Caleb is an EE M.S. student at Stanford. He received his B.S. in Computer Engineering from UCLA in 2022. Previously, he has interned as an FPGA designer at Jane Street and as an IP designer at Apple and Intel.<br>           
+        <b>Research:</b> His research relates to the generation and verification of the compiler for CGRA programs. In the fall of 2022, he utilized SMT-based tools to verify the functionality of pipelined compute mappings to CGRA processing elements (PEs). This year, he focuses on improving rewrite rule synthesis to enable many-to-many rewrite rules.
+      </td>
+    </tr>
   </tbody>
 </table>