Able to generate RTL and pass PW tb

StanfordAHA · Nov 4, 2024 · 95f7677 · 95f7677
1 parent 698a1c1
commit 95f7677
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/archipelago b/archipelago
diff --git a/canal b/canal
diff --git a/garnet b/garnet
diff --git a/lake b/lake
+11 −0		canal/circuit.py
+7 −0		canal/cyclone.py
+5 −0		canal/interconnect.py
+43 −1		canal/util.py
+29 −4		cgra/util_onyx.py
+34 −5		cgra/wiring_onyx.py
+56 −3		garnet.py
+2 −2		global_buffer/design/global_buffer.py
+3 −0		global_buffer/design/global_buffer_parameter.py
+12 −5		global_buffer/io_placement.py
+1 −0		global_controller/global_controller_genesis2.py
+4 −2		global_controller/global_controller_magma.py
+2 −1		global_controller/rtl/genesis/glc_axi_addrmap.svp
+4 −3		global_controller/rtl/genesis/glc_jtag_ctrl.svp
+3 −2		global_controller/rtl/genesis/global_controller.svp
+12 −7		memory_core/memtile_util.py
+137 −0		memory_core/mu2f_io_core_rv.py
+22 −5		passes/interconnect_port_pass/interconnect_port_pass.py
+10 −3		tests/test_app/lib/map.c
+4 −1		tests/test_app/lib/parser.c
+20 −8		tests/test_app/tb/environment.sv
+43 −1		tests/test_app/tb/top.sv