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Describe the usage of XSim. #230
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@@ -59,6 +59,26 @@ How SpinalHDL simulates the hardware with Synopsys VCS backend | |
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Before using VCS as the simulation backend, make sure that you have checked your system environment as :ref:`VCS environment<vcs_env>`. | ||
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How SpinalHDL simulates the hardware with Xilinx XSim backend | ||
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1. SpinalHDL generates a Verilog/VHDL (depended on your choice) hardware model of the DUT. | ||
2. The HDL model is loaded in the simulator. | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. via hand wavey magic ? LOL Can more be said about this part, I think out of all of the steps this is the one the reader is looking for as much support as possible to resolve. What does this step mean ? it is loaded via GUI (Vivado) or command-line (how to get correct environment setup, if you installed Vivado as per Xilinx instructions) ? How do you use your msys2 support package(s) ? These are 3 ways I can think a reader might want to understand. For example what does a SpinalSim config look like for XSim ? what important extra flags might be useful to know, do you have to do anything special to ensure the Xilinx primitive catalog models are available to the simulation ? is the LD_LIBRARY_PATH setup a concern at runtime ? |
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3. The communication between the simulation and the JVM is established through shared memory. The commands are issued to the simulator using XSI. | ||
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**Advantages:** | ||
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* Support Xilinx built-in primitives and cores. | ||
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**Limitations:** | ||
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* Xilinx XSim is a **commercial** tool installed with Vivado. It is closed source and subject to licensing terms to use. You have to own the licenses to **legally** use it. | ||
* Vivado versions prior to 2019.1 do not work properly. | ||
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Before using XSim as the simulation backend, make sure that you have done following steps. | ||
1. Define VIVADO_HOME environment variable to specify where your vivado located. ex `export VIVADO_HOME=/d/Xilinx/Vivado/2022.1` (under MSYS2). | ||
2. Make sure two vivado path is inside the PATH. For Windows MSYS2 user, run shell command like `export PATH=$PATH:$VIVADO_HOME/bin:$VIVADO_HOME/lib/win64.o`. For Linux user just source the Vivado's settings64.sh file located at `VIVADO_HOME`. | ||
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This is more like the meat into what the reader is looking for :) More of this :) Is it possible to provide a code snippet of a minimal SpinalSim testbench which can be used as an installation and setup check ? It helps the reader to know if they run this program and they have everything setup, it should work. Then in the future with feedback we can address any common error messages seen in the setup and how to fix. Getting the environment working is probably why the reader is looking at the documentation here. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I don't think this page is a good place to write this details. May be this location is better. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. It is the specific detail needed to make XSim work that would be captured here. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. So that would be more work on this. I just keep the consistency with other parts. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more.
You're right, a simulation tutorial for each simulation engine would be a good choice. |
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Performance | ||
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SpinalHDL generates industry standard HDL sources for XSim such as Verilog or VHDL (dependent on your elaboration choice) for the hardware model of the DUT.