update .pot files

source/locale/gettext/SpinalHDL/Libraries/Pipeline/introduction.pot

@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: SpinalHDL \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2024-02-19 09:02+0000\n"
+"POT-Creation-Date: 2024-02-19 22:32+0000\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <[email protected]>\n"
@@ -623,46 +623,46 @@ msgstr ""
 msgid "Here is how it can be done with this pipelining API :"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:639
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:646
 msgid "If then you generate this component like this :"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:652
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:659
 msgid "You will get a 4 stages separated by 3 layer of flip flop doing your processing :"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:657
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:664
 msgid "Note the generated hardware verilog is kinda clean (by my standards at least :P) :"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:772
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:779
 msgid "Also, you can easily tweak how many stages and where you want the processing to be done, for instance you may want to move the inversion hardware in the same stage as the adder. This can be done the following way :"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:786
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:793
 msgid "Then you may want to remove the output register stage :"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:802
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:809
 msgid "Simple CPU example"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:804
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:811
 msgid "Here is a simple/stupid 8 bits CPU example with :"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:806
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:813
 msgid "3 stages (fetch, decode, execute)"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:807
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:814
 msgid "embedded fetch memory"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:808
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:815
 msgid "add / jump / led /delay instructions"
 msgstr ""
 
-#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:879
+#: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:886
 msgid "Here is a simple testbench which implement a loop which will make the led counting up."
 msgstr ""