Merge branch 'SpinalHDL:master' into master

source/SpinalHDL/Getting Started/Install and setup.rst

@@ -19,6 +19,12 @@ Before you download the SpinalHDL tools, you need to install a Scala environment
   environment
 * `SBT <https://www.scala-sbt.org/download.html>`_, a Scala build tool
 
+These tools enable to use Spinal; but without any other tools, it is limited to
+code generation.
+
+Linux Installation
+----------------------
+
 For instance, to install them on the Debian distribution:
 
 .. code-block:: sh
@@ -31,10 +37,37 @@ For instance, to install them on the Debian distribution:
    sudo apt-get update
    sudo apt-get install sbt
 
-These tools enable to use Spinal; but without any other tools, it is limited to
-code generation.
+Mac OS X Installation
+----------------------
+You can use homebrew to install on Mac OS X.  By default homebrew installs Java 21, but the  SpinalHDL tutorial 
+SpinalTemplateSbt uses Scala version 2.12.16, which is not supported by Java 21 (17 is still the recommended LTS version, https://whichjdk.com/). So to install Java version 1.7 do:
+
+.. code-block:: sh
+
+    brew install openjdk@17
+
+And then add this to your path.
+
+.. code-block:: sh
+
+   export PATH="/opt/homebrew/opt/openjdk@17/bin:$PATH"
+
+To manage multiple versions of Java, it is also essential to have jenv installed.
+
+.. code-block:: sh
+
+   brew install jenv
+
+Jenv added these lines to my .bash_profile
+
+.. code-block:: sh
 
+   export PATH="$HOME/.jenv/bin:$PATH"
+   eval "$(jenv init -)"
 
+If this works for you, please let us know.  If this does not work for you, you can read the github issue about Mac o SX installation here. 
+https://github.com/SpinalHDL/SpinalHDL/issues/1216
+
 Installing SBT in an internet-free environment
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 

source/SpinalHDL/Getting Started/SBT.rst

@@ -40,9 +40,9 @@ if you type ``runMain``, space, and tab, you should get this:
 .. code-block::
 
    sbt:SpinalTemplateSbt> runMain 
-;                               projectname.MyTopLevelVerilog
-projectname.MyTopLevelFormal    projectname.MyTopLevelVhdl
-projectname.MyTopLevelSim
+      ;                               projectname.MyTopLevelVerilog
+      projectname.MyTopLevelFormal    projectname.MyTopLevelVhdl
+      projectname.MyTopLevelSim
 
 The autocompletion suggests all things that can be run. Let's run the Verilog
 generation for instance:

source/SpinalHDL/Structuring/clock_domain.rst

@@ -52,7 +52,8 @@ This definition takes five parameters:
      - The goal of this signal is to disable the clock on the whole clock domain without having to manually implement that on each synchronous element
      - null
    * - ``frequency``
-     - Allows you to specify the frequency of the given clock domain and later read it in your design
+     - Allows you to specify the frequency of the given clock domain and later read it in your design.
+       This parameter does not generate and PLL or other hardware to control the frequency
      - UnknownFrequency
    * - ``config``
      - Specify the polarity of signals and the nature of the reset
@@ -248,6 +249,12 @@ Once created, you have to assign the ``ClockDomain``'s signals, as shown in the
      }
    }
 
+.. warning::
+   In other components then the one you created the ClockDomain in, you must not use ``.clock`` and ``.reset``,
+   but ``.readClockWire`` and ``.readResetWire`` as listed below. For the global ClockDomain you must always
+   use those ``.readXXX`` functions.
+
+
 External clock
 ^^^^^^^^^^^^^^
 
@@ -273,7 +280,7 @@ The arguments to the ``ClockDomain.external`` function are exactly the same as i
        val result = out UInt (4 bits)
      }
 
-     // On the top level you have two signals  :
+     // On the top level you have two signals  :
      //     myClockName_clk and myClockName_reset
      val myClockDomain = ClockDomain.external("myClockName")
 
@@ -347,10 +354,10 @@ The returned ``ClockDomain`` instance has the following functions that can be ca
      - Return a signal derived from the clock signal
      - Bool
    * - readResetWire
-     - Return a signal derived from the soft reset signal
+     - Return a signal derived from the reset signal
      - Bool
    * - readSoftResetWire
-     - Return a signal derived from the reset signal
+     - Return a signal derived from the soft reset signal
      - Bool
    * - readClockEnableWire
      - Return a signal derived from the clock enable signal
@@ -365,7 +372,6 @@ The returned ``ClockDomain`` instance has the following functions that can be ca
      - Return True when the clock enable is active
      - Bool
 
-
 An example is included below where a UART controller uses the frequency specification to set its clock divider:
 
 .. code-block:: scala

source/conf.py

@@ -231,6 +231,7 @@
 
 #Option for linkcheck
 linkcheck_anchors=False
+tls_verify = False # disable since Intel urls don't verify on github infra
 
 # Whitelist pattern for tags (set to None to ignore all tags)
 smv_tag_whitelist = r'^.*$'