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Merge pull request #225 from andreasWallner/variable_assign_only_for_…
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Add note that \= only works for comb signals
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Dolu1990 authored Oct 27, 2023
2 parents e160aa3 + f733704 commit ab4d3f3
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2 changes: 1 addition & 1 deletion source/SpinalHDL/Semantic/assignments.rst
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Expand Up @@ -12,7 +12,7 @@ There are multiple assignment operators:
* - ``:=``
- Standard assignment, equivalent to ``<=`` in VHDL/Verilog.
* - ``\=``
- Equivalent to ``:=`` in VHDL and ``=`` in Verilog. The value is updated instantly in-place.
- Equivalent to ``:=`` in VHDL and ``=`` in Verilog. The value is updated instantly in-place. Only works with combinational signals, does not work with registers.
* - ``<>``
- Automatic connection between 2 signals or two bundles of the same type. Direction is inferred by using signal direction (in/out). (Similar behavior to ``:=``\ )

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