update .pot files

source/locale/gettext/SpinalHDL/Simulation/clock.pot

@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: SpinalHDL \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2024-08-19 09:12+0000\n"
+"POT-Creation-Date: 2024-10-07 02:44+0000\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <[email protected]>\n"
@@ -34,7 +34,7 @@ msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:14
 #: ../../SpinalHDL/Simulation/clock.rst:48
-#: ../../SpinalHDL/Simulation/clock.rst:84
+#: ../../SpinalHDL/Simulation/clock.rst:88
 msgid "Description"
 msgstr ""
 
@@ -125,7 +125,7 @@ msgid "Wait API"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:41
-#: ../../SpinalHDL/Simulation/clock.rst:77
+#: ../../SpinalHDL/Simulation/clock.rst:81
 msgid "Below is a list of ``ClockDomain`` utilities that you can use to wait for a given event from the domain:"
 msgstr ""
 
@@ -166,133 +166,149 @@ msgid "Same as ``waitRisingEdge`` but for the edge level specified by the ``Cloc
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:57
-msgid "``waitRisingEdgeWhere(condition)``"
+msgid "``waitInactiveEdge([cyclesCount])``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:58
-msgid "Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be true when the rising edge occurs"
+msgid "Same as ``waitFallingEdge`` but for the edge level specified by the ``ClockDomainConfig``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:59
-msgid "``waitFallingEdgeWhere(condition)``"
+msgid "``waitRisingEdgeWhere(condition)``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:60
-msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge"
+msgid "Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be true when the rising edge occurs"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:61
-msgid "``waitActiveEdgeWhere(condition)``"
+msgid "``waitFallingEdgeWhere(condition)``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:62
-msgid "Same as ``waitRisingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``"
+msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:63
-msgid "``waitSamplingWhere(condition) : Boolean``"
+msgid "``waitActiveEdgeWhere(condition)``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:64
-msgid "Wait until a clockdomain sampled and the given condition is true"
+msgid "Same as ``waitRisingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:65
-msgid "``waitSamplingWhere(timeout)(condition) : Boolean``"
+msgid "``waitInactiveEdgeWhere(condition)``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:66
-msgid "Same as waitSamplingWhere defined above, but will never block more than timeout cycles. Return true if the exit condition came from the timeout"
+msgid "Same as ``waitFallingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:67
+msgid "``waitSamplingWhere(condition) : Boolean``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:68
+msgid "Wait until a clockdomain sampled and the given condition is true"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:69
+msgid "``waitSamplingWhere(timeout)(condition) : Boolean``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:70
+msgid "Same as waitSamplingWhere defined above, but will never block more than timeout cycles. Return true if the exit condition came from the timeout"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:74
 msgid "All the functionality of the wait API can only be called directly from inside a thread, and not from a callback executed via the Callback API."
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:75
+#: ../../SpinalHDL/Simulation/clock.rst:79
 msgid "Callback API"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:83
+#: ../../SpinalHDL/Simulation/clock.rst:87
 msgid "ClockDomain callback functions"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:85
+#: ../../SpinalHDL/Simulation/clock.rst:89
 msgid "``onNextSampling { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:86
+#: ../../SpinalHDL/Simulation/clock.rst:90
 msgid "Execute the callback code only once on the next ``ClockDomain`` sample (active edge + reset off + clock enable on)"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:87
+#: ../../SpinalHDL/Simulation/clock.rst:91
 msgid "``onSamplings { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:88
+#: ../../SpinalHDL/Simulation/clock.rst:92
 msgid "Execute the callback code each time the ``ClockDomain`` sample (active edge + reset off + clock enable on)"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:89
+#: ../../SpinalHDL/Simulation/clock.rst:93
 msgid "``onActiveEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:90
+#: ../../SpinalHDL/Simulation/clock.rst:94
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates its configured edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:91
+#: ../../SpinalHDL/Simulation/clock.rst:95
 msgid "``onEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:92
+#: ../../SpinalHDL/Simulation/clock.rst:96
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising or falling edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:93
+#: ../../SpinalHDL/Simulation/clock.rst:97
 msgid "``onRisingEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:94
+#: ../../SpinalHDL/Simulation/clock.rst:98
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:95
+#: ../../SpinalHDL/Simulation/clock.rst:99
 msgid "``onFallingEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:96
+#: ../../SpinalHDL/Simulation/clock.rst:100
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a falling edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:97
+#: ../../SpinalHDL/Simulation/clock.rst:101
 msgid "``onSamplingWhile { callback : Boolean }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:98
+#: ../../SpinalHDL/Simulation/clock.rst:102
 msgid "Same as onSampling, but you can stop it (forever) by letting the callback returning false"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:102
+#: ../../SpinalHDL/Simulation/clock.rst:106
 msgid "Default ClockDomain"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:104
+#: ../../SpinalHDL/Simulation/clock.rst:108
 msgid "You can access the default ``ClockDomain`` of your toplevel as shown below:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:120
+#: ../../SpinalHDL/Simulation/clock.rst:124
 msgid "Note that you can also directly fork a standard reset/clock process:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:126
+#: ../../SpinalHDL/Simulation/clock.rst:130
 msgid "An example of how to wait for a rising edge on the clock:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:134
+#: ../../SpinalHDL/Simulation/clock.rst:138
 msgid "New ClockDomain"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:136
+#: ../../SpinalHDL/Simulation/clock.rst:140
 msgid "If your toplevel defines some clock and reset inputs which aren't directly integrated into their ``ClockDomain``, you can define their corresponding ``ClockDomain`` directly in the testbench:"
 msgstr ""