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Merge pull request jijingg#23 from volatile-static/patch-1
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add examples
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@jijingg
jijingg authored Jun 25, 2022
2 parents 755d2e5 + fe4aae8 commit 4410bd3
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87 changes: 74 additions & 13 deletions 4.1-Spinal-Example-Simple-ones.ipynb
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Expand Up @@ -29,7 +29,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
"## [APB3 definition](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Simple%20ones/apb3.html)\n",
"## [APB3 definition](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Simple%20ones/apb3.html)\n",
"#### Implementation"
]
},
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"cell_type": "markdown",
"metadata": {},
"source": [
"## [Carry adder](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Simple%20ones/carry_adder.html)"
"## [Carry adder](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Simple%20ones/carry_adder.html)"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"This example defines a component with inputs `a` and `b`, and a `result` output. At any time, `result` will be the sum of `a` and `b` (combinatorial). This sum is manually done by a carry adder logic."
]
},
{
Expand All @@ -122,7 +129,7 @@
" }\n",
"\n",
" var c = False //Carry, like a VHDL variable\n",
" for (i <- 0 until size) {\n",
" for (i <- 0 until size) { // 0 <= i < size\n",
" //Create some intermediate value in the loop scope.\n",
" val a = io.a(i)\n",
" val b = io.b(i)\n",
Expand All @@ -140,7 +147,14 @@
"cell_type": "markdown",
"metadata": {},
"source": [
"## [Color summing](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Simple%20ones/color_summing.html)"
"Note that only variables who declared with `var` support the operator `\\=`."
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"## [Color summing](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Simple%20ones/color_summing.html)"
]
},
{
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"cell_type": "markdown",
"metadata": {},
"source": [
"## [Counter with clear](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Simple%20ones/counter_with_clear.html)"
"## [Counter with clear](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Simple%20ones/counter_with_clear.html)"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"This example defines a component with a `clear` input and a `value` output. Each clock cycle, the `value` output is incrementing, but when `clear` is high, `value` is cleared."
]
},
{
Expand Down Expand Up @@ -220,7 +241,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
"## [PLL BlackBox and reset controller](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Simple%20ones/pll_resetctrl.html)\n",
"## [PLL BlackBox and reset controller](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Simple%20ones/pll_resetctrl.html)\n",
"#### The PLL BlackBox definition"
]
},
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"cell_type": "markdown",
"metadata": {},
"source": [
"## [RGB to gray](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Simple%20ones/rgb_to_gray.html)"
"## [RGB to gray](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Simple%20ones/rgb_to_gray.html)"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"Let’s imagine a component that converts an RGB color into a gray one, and then writes it into external memory.\n",
"\n",
"| io name | Direction | Description |\n",
"|-|-|-|\n",
"| clear | in | Clear all internal registers |\n",
"| r,g,b | in | Color inputs |\n",
"| wr | out | Memory write |\n",
"| address | out | Memory address, incrementing each cycle |\n",
"| data | out | Memory data, gray level |"
]
},
{
Expand Down Expand Up @@ -342,7 +378,16 @@
"cell_type": "markdown",
"metadata": {},
"source": [
"## [Sinus rom](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Simple%20ones/sinus_rom.html)"
"## [Sinus rom](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Simple%20ones/sinus_rom.html)"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"Let’s imagine that you want to generate a sine wave and also have a filtered version of it (which is completely useless in practical, but let’s do it as an example).\n",
"\n",
"![](./source/sin.svg)"
]
},
{
Expand All @@ -351,26 +396,42 @@
"metadata": {},
"outputs": [],
"source": [
"import scala.math\n",
"\n",
"class TopLevel(resolutionWidth: Int, sampleCount: Int) extends Component {\n",
" val io = new Bundle {\n",
" val sin = out SInt(resolutionWidth bits)\n",
" val sinFiltred = out SInt(resolutionWidth bits)\n",
" }\n",
"\n",
" def sinTable = for(sampleIndex <- 0 until sampleCount) yield {\n",
" val sinValue = Math.sin(2 * Math.PI * sampleIndex / sampleCount)\n",
" S((sinValue * ((1<<resolutionWidth)/2-1)).toInt,resolutionWidth bits)\n",
" val sinValue = math.sin(2 * math.Pi * sampleIndex / sampleCount)\n",
" S((sinValue * ((1<<resolutionWidth)/2-1)).toInt, resolutionWidth bits)\n",
" }\n",
"\n",
" val rom = Mem(SInt(resolutionWidth bits),initialContent = sinTable)\n",
" val phase = Reg(UInt(log2Up(sampleCount) bits)) init(0)\n",
" phase := phase + 1\n",
" phase := phase + 1 // counter\n",
"\n",
" io.sin := rom.readSync(phase)\n",
" io.sinFiltred := RegNext(io.sinFiltred - (io.sinFiltred >> 5) + (io.sin >> 5)) init(0)\n",
"}\n",
"\n",
"showRtl(new TopLevel(32, 64))"
"showRtl(new TopLevel(24, 256))"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"![schematic](./source/sine.png)"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"And then you can find the contents of rom at a [binary file](./rtl/TopLevel.v_toplevel_rom.bin)."
]
}
],
Expand All @@ -386,7 +447,7 @@
"mimetype": "text/x-scala",
"name": "scala",
"nbconvert_exporter": "script",
"version": "2.11.12"
"version": "2.12.11"
}
},
"nbformat": 4,
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6 changes: 3 additions & 3 deletions 4.2-Spinal-Example-Intermediate-ones.ipynb
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Expand Up @@ -29,7 +29,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
"## [Fractal calculator](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Intermediates%20ones/fractal.html)\n",
"## [Fractal calculator](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Intermediates%20ones/fractal.html)\n",
"#### Elaboration parameters (Generics)"
]
},
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"cell_type": "markdown",
"metadata": {},
"source": [
"## [UART](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Intermediates%20ones/uart.html)\n",
"## [UART](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Intermediates%20ones/uart.html)\n",
"#### Controller construction parameters"
]
},
Expand Down Expand Up @@ -633,7 +633,7 @@
"cell_type": "markdown",
"metadata": {},
"source": [
"## [VGA](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Examples/Intermediates%20ones/vga.html)\n",
"## [VGA](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Intermediates%20ones/vga.html)\n",
"#### RGB color"
]
},
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19 changes: 10 additions & 9 deletions source/load-spinal.sc
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Expand Up @@ -15,32 +15,33 @@ import spinal.lib._
import spinal.core.sim._

implicit class SpinalReportExtend(sp :SpinalReport[Component]) {
def getRtlString_local():String = {
assert(sp.generatedSourcesPaths.size == 1)
def getRtlString_local(): String = {
assert(sp.generatedSourcesPaths.size > 0)
scala.io.Source.fromFile(sp.generatedSourcesPaths.head).mkString
}
}

val spcfg = SpinalConfig(
defaultConfigForClockDomains = ClockDomainConfig(clockEdge = RISING,
val spcfg = SpinalConfig(
defaultConfigForClockDomains = ClockDomainConfig(
clockEdge = RISING,
resetKind = ASYNC,
resetActiveLevel = LOW
),
headerWithDate = true,
removePruned = false,
anonymSignalPrefix = "t",
mergeAsyncProcess = true ,
targetDirectory="rtl/"
mergeAsyncProcess = true,
targetDirectory = "rtl/"
)

def showRtl(dut: => Component, mode:SpinalMode = `Verilog`) = {
def showRtl(dut: => Component, mode: SpinalMode = `Verilog`) = {
println(spcfg.copy(mode = mode).generate(dut).getRtlString_local)
}

def showVhdl(dut: => Component) = showRtl(dut,VHDL)
def showVhdl(dut: => Component) = showRtl(dut, VHDL)

@deprecated("Deprecated, showRtl is recommended", "spinal-bootcamp 0.1.0")
def showVerilog(dut: => Component, moduleName:String) = {
def showVerilog(dut: => Component, moduleName: String) = {
spcfg.copy(mode = Verilog).generate(dut)
println(scala.io.Source.fromFile("rtl/"+moduleName+".v").mkString)
}
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