Cleanup 02of20: import local ref change

AhbLite3.py

@@ -4,18 +4,18 @@
 from cocotb.result import TestFailure
 from cocotb.triggers import RisingEdge, Edge
 
-from cocotblib.misc import log2Up, BoolRandomizer, assertEquals
+from .misc import log2Up, BoolRandomizer, assertEquals
 
 
 def AhbLite3MasterIdle(ahb):
- ahb.HADDR <= 0
- ahb.HWRITE <= 0
- ahb.HSIZE <= 0
- ahb.HBURST <= 0
- ahb.HPROT <= 0
- ahb.HTRANS <= 0
- ahb.HMASTLOCK <= 0
- ahb.HWDATA <= 0
+ ahb.HADDR.value = 0
+ ahb.HWRITE.value = 0
+ ahb.HSIZE.value = 0
+ ahb.HBURST.value = 0
+ ahb.HPROT.value = 0
+ ahb.HTRANS.value = 0
+ ahb.HMASTLOCK.value = 0
+ ahb.HWDATA.value = 0
 
 
 
@@ -108,29 +108,29 @@ def __init__(self,ahb,transactor,clk,reset):
  @cocotb.coroutine
  def stim(self):
  ahb = self.ahb
- ahb.HADDR <= 0
- ahb.HWRITE <= 0
- ahb.HSIZE <= 0
- ahb.HBURST <= 0
- ahb.HPROT <= 0
- ahb.HTRANS <= 0
- ahb.HMASTLOCK <= 0
- ahb.HWDATA <= 0
+ ahb.HADDR.value = 0
+ ahb.HWRITE.value = 0
+ ahb.HSIZE.value = 0
+ ahb.HBURST.value = 0
+ ahb.HPROT.value = 0
+ ahb.HTRANS.value = 0
+ ahb.HMASTLOCK.value = 0
+ ahb.HWDATA.value = 0
  HWDATAbuffer = 0
  while True:
  for trans in self.transactor.getTransactions():
  yield RisingEdge(self.clk)
  while int(self.ahb.HREADY) == 0:
  yield RisingEdge(self.clk)
 
- ahb.HADDR <= trans.HADDR
- ahb.HWRITE <= trans.HWRITE
- ahb.HSIZE <= trans.HSIZE
- ahb.HBURST <= trans.HBURST
- ahb.HPROT <= trans.HPROT
- ahb.HTRANS <= trans.HTRANS
- ahb.HMASTLOCK <= trans.HMASTLOCK
- ahb.HWDATA <= HWDATAbuffer
+ ahb.HADDR.value = trans.HADDR
+ ahb.HWRITE.value = trans.HWRITE
+ ahb.HSIZE.value = trans.HSIZE
+ ahb.HBURST.value = trans.HBURST
+ ahb.HPROT.value = trans.HPROT
+ ahb.HTRANS.value = trans.HTRANS
+ ahb.HMASTLOCK.value = trans.HMASTLOCK
+ ahb.HWDATA.value = HWDATAbuffer
  HWDATAbuffer = trans.HWDATA
 
 class AhbLite3Terminaison:
@@ -145,8 +145,8 @@ def __init__(self,ahb,clk,reset):
  @cocotb.coroutine
  def stim(self):
  randomizer = BoolRandomizer()
- self.ahb.HREADY <= 1
- self.ahb.HSEL <= 1
+ self.ahb.HREADY.value = 1
+ self.ahb.HSEL.value = 1
  while True:
  yield RisingEdge(self.clk)
  self.randomHREADY = randomizer.get()
@@ -159,7 +159,7 @@ def combEvent(self):
  self.doComb()
 
  def doComb(self):
- self.ahb.HREADY <= (self.randomHREADY and (int(self.ahb.HREADYOUT) == 1))
+ self.ahb.HREADY.value = (self.randomHREADY and (int(self.ahb.HREADYOUT) == 1))
 
 
 class AhbLite3MasterReadChecker:
@@ -210,7 +210,7 @@ def __init__(self,ahb,base,size,clk,reset):
  @cocotb.coroutine
  def stimReady(self):
  randomizer = BoolRandomizer()
- self.ahb.HREADYOUT <= 1
+ self.ahb.HREADYOUT.value = 1
  busy = False
  while True:
  yield RisingEdge(self.clk)
@@ -222,16 +222,16 @@ def stimReady(self):
  raise TestFailure("HREADYOUT == 0 but HREADY == 1 ??? " + self.ahb.HREADY._name)
  busy = busyNew
  if (busy):
- self.ahb.HREADYOUT <= randomizer.get() # make some random delay for NONSEQ and SEQ requests
+ self.ahb.HREADYOUT.value = randomizer.get()  # make some random delay for NONSEQ and SEQ requests
  else:
- self.ahb.HREADYOUT <= 1 # IDLE and BUSY require 0 WS
+ self.ahb.HREADYOUT.value = 1  # IDLE and BUSY require 0 WS
 
  @cocotb.coroutine
  def stim(self):
  ahb = self.ahb
- ahb.HREADYOUT <= 1
- ahb.HRESP <= 0
- ahb.HRDATA <= 0
+ ahb.HREADYOUT.value = 1
+ ahb.HRESP.value = 0
+ ahb.HRDATA.value = 0
  valid = 0
  while True:
  yield RisingEdge(self.clk)
@@ -252,7 +252,7 @@ def stim(self):
  address = int(ahb.HADDR)
  addressOffset = address % (len(ahb.HWDATA)//8)
 
- ahb.HRDATA <= 0
+ ahb.HRDATA.value = 0
  if valid == 1:
  if trans >= 2:
  if write == 0:
@@ -261,4 +261,4 @@ def stim(self):
  data |= self.ram[address-self.base + idx] << (8*(addressOffset + idx))
  # print("read %x with %x" % (address + idx, self.ram[address-self.base + idx]))
  # print(str(data))
- ahb.HRDATA <= int(data)
+ ahb.HRDATA.value = int(data)

Apb3.py

@@ -5,7 +5,7 @@
 from cocotb.result import TestFailure, ReturnValue
 from cocotb.triggers import RisingEdge, Edge
 
-from cocotblib.misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal
+from .misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal
 
 
 class Apb3:
@@ -20,7 +20,7 @@ def __init__(self, dut, name, clk = None):
  self.PRDATA = dut.__getattr__(name + "_PRDATA")
 
  def idle(self):
- self.PSEL <= 0
+ self.PSEL.value = 0
 
  @coroutine
  def delay(self, cycle):
@@ -29,16 +29,16 @@ def delay(self, cycle):
 
  @coroutine
  def write(self, address, data, sel = 1):
- self.PADDR <= address
- self.PSEL <= sel
- self.PENABLE <= False
- self.PWRITE <= True
- self.PWDATA <= data
+ self.PADDR.value = address
+ self.PSEL.value = sel
+ self.PENABLE.value = False
+ self.PWRITE.value = True
+ self.PWDATA.value = data
  yield RisingEdge(self.clk)
- self.PENABLE <= True
+ self.PENABLE.value = True
  yield waitClockedCond(self.clk, lambda : self.PREADY == True)
  randSignal(self.PADDR)
- self.PSEL <= 0
+ self.PSEL.value = 0
  randSignal(self.PENABLE)
  randSignal(self.PWRITE)
  randSignal(self.PWDATA)
@@ -51,16 +51,16 @@ def writeMasked(self, address, data, mask, sel = 1):
 
  @coroutine
  def read(self, address, sel=1):
- self.PADDR <= address
- self.PSEL <= sel
- self.PENABLE <= False
- self.PWRITE <= False
+ self.PADDR.value = address
+ self.PSEL.value = sel
+ self.PENABLE.value = False
+ self.PWRITE.value = False
  randSignal(self.PWDATA)
  yield RisingEdge(self.clk)
- self.PENABLE <= True
+ self.PENABLE.value = True
  yield waitClockedCond(self.clk, lambda: self.PREADY == True)
  randSignal(self.PADDR)
- self.PSEL <= 0
+ self.PSEL.value = 0
  randSignal(self.PENABLE)
  randSignal(self.PWRITE)
  raise ReturnValue(int(self.PRDATA))

Axi4.py

@@ -1,11 +1,11 @@
 import random
 from queue import Queue
 
-from cocotblib.Phase import PHASE_SIM, Infrastructure
-from cocotblib.Scorboard import ScorboardOutOfOrder
-from cocotblib.misc import BoolRandomizer, log2Up, randBits
+from .Phase import PHASE_SIM, Infrastructure
+from .Scorboard import ScorboardOutOfOrder
+from .misc import BoolRandomizer, log2Up, randBits
 
-from cocotblib.Stream import Stream, Transaction, StreamDriverSlave, StreamDriverMaster, StreamMonitor
+from .Stream import Stream, Transaction, StreamDriverSlave, StreamDriverMaster, StreamMonitor
 
 
 class Axi4:
@@ -74,8 +74,8 @@ def __init__(self,name,parent,axi,addressWidth,clk,reset):
  StreamDriverMaster(axi.w, self.genWriteData, clk, reset)
  StreamMonitor(axi.r, self.onReadRsp, clk, reset)
  StreamMonitor(axi.b, self.onWriteRsp, clk, reset)
- axi.w.payload.last <= 0
- axi.r.payload.last <= 0
+ axi.w.payload.last.value = 0
+ axi.r.payload.last.value = 0
 
  def freeReservatedAddresses(self,uut,ref,equal):
  self.reservedAddresses.pop(ref,None)

ClockDomain.py

@@ -50,12 +50,12 @@ def start(self):
  cocotb.fork(self._waitEndReset())
 
  if self.reset:
- self.reset <= self.typeReset
+ self.reset.value = self.typeReset
 
  yield Timer(self.halfPeriod * 5)
 
  if self.reset:
- self.reset <= int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0)
+ self.reset.value = int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0)
 
 
  ##########################################################################
@@ -70,9 +70,9 @@ def stop(self):
  @cocotb.coroutine
  def _clkGen(self):
  while True:
- self.clk <= 0
+ self.clk.value = 0
  yield Timer(self.halfPeriod)
- self.clk <= 1
+ self.clk.value = 1
  yield Timer(self.halfPeriod)
 
 

Flow.py

@@ -1,6 +1,6 @@
 import cocotb
 from cocotb.triggers import RisingEdge, Event
-from cocotblib.misc import Bundle
+from .misc import Bundle
 
 
 ###############################################################################

Scorboard.py

@@ -3,7 +3,7 @@
 import cocotb
 from cocotb.result import TestFailure
 
-from cocotblib.Phase import Infrastructure, PHASE_CHECK_SCORBOARDS
+from .Phase import Infrastructure, PHASE_CHECK_SCORBOARDS
 
 
 class ScorboardInOrder(Infrastructure):

Spi.py

@@ -5,8 +5,8 @@
 from cocotb.result import TestFailure, ReturnValue
 from cocotb.triggers import RisingEdge, Edge, Timer
 
-from cocotblib.TriState import TriStateOutput
-from cocotblib.misc import log2Up, BoolRandomizer, assertEquals, testBit
+from .TriState import TriStateOutput
+from .misc import log2Up, BoolRandomizer, assertEquals, testBit
 
 
 class SpiMaster:
@@ -40,42 +40,42 @@ def __init__(self, spi):
  self.dataWidth = 8
 
  def init(self, cpol, cpha, baudrate, dataWidth = 8):
- self.spi.ss <= True
+ self.spi.ss.value = True
  self.cpol = cpol
  self.cpha = cpha
  self.baudPeriode = baudrate
  self.dataWidth = dataWidth
- self.spi.sclk <= cpol
+ self.spi.sclk.value = cpol
 
  @coroutine
  def enable(self):
- self.spi.ss <= False
+ self.spi.ss.value = False
  yield Timer(self.baudPeriode)
 
  @coroutine
  def disable(self):
  yield Timer(self.baudPeriode)
- self.spi.ss <= True
+ self.spi.ss.value = True
  yield Timer(self.baudPeriode)
 
  @coroutine
  def exchange(self, masterData):
  buffer = ""
  if not self.cpha:
  for i in range(self.dataWidth):
- self.spi.mosi <= testBit(masterData, self.dataWidth - 1 - i)
+ self.spi.mosi.value = testBit(masterData, self.dataWidth - 1 - i)
  yield Timer(self.baudPeriode >> 1)
  buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x"
- self.spi.sclk <= (not self.cpol)
+ self.spi.sclk.value = (not self.cpol)
  yield Timer(self.baudPeriode >> 1)
- self.spi.sclk <= (self.cpol)
+ self.spi.sclk.value = (self.cpol)
  else:
  for i in range(self.dataWidth):
- self.spi.mosi <= testBit(masterData, self.dataWidth -1 - i)
- self.spi.sclk <= (not self.cpol)
+ self.spi.mosi.value = testBit(masterData, self.dataWidth -1 - i)
+ self.spi.sclk.value = (not self.cpol)
  yield Timer(self.baudPeriode >> 1)
  buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x"
- self.spi.sclk <= (self.cpol)
+ self.spi.sclk.value = (self.cpol)
  yield Timer(self.baudPeriode >> 1)
 
  raise ReturnValue(buffer)

Stream.py

@@ -3,10 +3,10 @@
 import types
 from cocotb.result import TestFailure
 from cocotb.triggers import RisingEdge, Timer, Event
-from cocotblib.Phase import Infrastructure, PHASE_WAIT_TASKS_END
-from cocotblib.Scorboard import ScorboardInOrder
+from .Phase import Infrastructure, PHASE_WAIT_TASKS_END
+from .Scorboard import ScorboardInOrder
 
-from cocotblib.misc import Bundle, BoolRandomizer
+from .misc import Bundle, BoolRandomizer
 
 
 class Stream:
@@ -94,11 +94,11 @@ def __init__(self,stream,transactor,clk,reset):
  @cocotb.coroutine
  def stim(self):
  stream = self.stream
- stream.valid <= 0
+ stream.valid.value = 0
  while True:
  yield RisingEdge(self.clk)
  if int(stream.valid) == 1 and int(stream.ready) == 1:
- stream.valid <= 0
+ stream.valid.value = 0
  for i in range(nextDelay):
  yield RisingEdge(self.clk)
 
@@ -112,12 +112,12 @@ def stim(self):
  nextDelay = trans.nextDelay
  else:
  nextDelay = 0
- stream.valid <= 1
+ stream.valid.value = 1
 
  for name in stream.payload.nameToElement:
  if hasattr(trans,name) == False:
  raise Exception("Missing element in bundle :" + name)
- e = stream.payload.nameToElement[name] <= getattr(trans,name)
+ e = stream.payload.nameToElement[name].value = getattr(trans,name)
 
 
 
@@ -132,10 +132,10 @@ def __init__(self,stream,clk,reset):
  @cocotb.coroutine
  def stim(self):
  stream = self.stream
- stream.ready <= 1
+ stream.ready.value = 1
  while True:
  yield RisingEdge(self.clk)
- stream.ready <= self.randomizer.get()
+ stream.ready.value = self.randomizer.get()
 
 
 def TransactionFromBundle(bundle):