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linux: port patches for dynamic configuration of network interfaces f…
…or 10G/25G
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patches/linux/0016-phy-lynx-28g-configure-more-equalization-params-for-.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,31 @@ | ||
| From 407de483856e9f24b857589992869debc547e50b Mon Sep 17 00:00:00 2001 | ||
| From: Ioana Ciornei <[email protected]> | ||
| Date: Wed, 5 Apr 2023 16:32:49 +0300 | ||
| Subject: [PATCH 16/18] phy: lynx-28g: configure more equalization params for | ||
| 10GBASER | ||
|
|
||
| We discovered that not all the equalization parameters for a lane were | ||
| configured upon an interface change. Configure the extra 2 registers | ||
| with the appropriate values for 10GBASE-R. | ||
|
|
||
| Signed-off-by: Ioana Ciornei <[email protected]> | ||
| --- | ||
| drivers/phy/freescale/phy-fsl-lynx-28g.c | 2 ++ | ||
| 1 file changed, 2 insertions(+) | ||
|
|
||
| diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c | ||
| index 85574f808eb9..a84192555b1a 100644 | ||
| --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c | ||
| +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c | ||
| @@ -326,6 +326,8 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) | ||
| iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); | ||
| iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id)); | ||
| iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); | ||
| + iowrite32(0x80000000, priv->base + LYNX_28G_LNaRCCR0(lane->id)); | ||
| + iowrite32(0x00408000, priv->base + LYNX_28G_LNaTTLCR0(lane->id)); | ||
| } | ||
|
|
||
| static int lynx_28g_power_off(struct phy *phy) | ||
| -- | ||
| 2.43.0 | ||
|
|
231 changes: 231 additions & 0 deletions
231
patches/linux/0017-phy-lynx-28g-add-support-for-25GBASER.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,231 @@ | ||
| From 7d62d489eaa5073602836bb4a0b02aaea21f3a8f Mon Sep 17 00:00:00 2001 | ||
| From: Ioana Ciornei <[email protected]> | ||
| Date: Wed, 5 Apr 2023 16:33:54 +0300 | ||
| Subject: [PATCH 17/18] phy: lynx-28g: add support for 25GBASER | ||
|
|
||
| Add support for 25GBASE-R in the Lynx 28G SerDes PHY driver. | ||
| This mainly means being able to determine if a PLL is able to support | ||
| the new interface type, to determine at probe time if a lane is | ||
| configured from RCW with this interface and to be able to reconfigure a | ||
| lane. | ||
|
|
||
| Signed-off-by: Ioana Ciornei <[email protected]> | ||
| --- | ||
| drivers/phy/freescale/phy-fsl-lynx-28g.c | 93 ++++++++++++++++++++++-- | ||
| 1 file changed, 87 insertions(+), 6 deletions(-) | ||
|
|
||
| diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c | ||
| index a84192555b1a..e7a9a6499fd0 100644 | ||
| --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c | ||
| +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c | ||
| @@ -22,7 +22,12 @@ | ||
| #define LYNX_28G_PCCC_USXGMII 0x1 | ||
| #define LYNX_28G_PCCC_SXGMII_DIS 0x0 | ||
|
|
||
| +#define LYNX_28G_PCCD 0x10b4 | ||
| +#define LYNX_28G_PCCD_25GBASER 0x1 | ||
| +#define LYNX_28G_PCCD_25GBASER_DIS 0x0 | ||
| + | ||
| #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) | ||
| +#define LYNX_28G_LNa_PCCD_OFFSET(lane) (4 * (lane->id)) | ||
|
|
||
| /* Per PLL registers */ | ||
| #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0) | ||
| @@ -42,6 +47,7 @@ | ||
| #define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO 0x0 | ||
| #define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000 | ||
| #define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000 | ||
| +#define LYNX_28G_PLLnCR1_FRATE_12G_25GVCO 0x16000000 | ||
|
|
||
| /* Per SerDes lane registers */ | ||
| /* Lane a General Control Register */ | ||
| @@ -49,9 +55,11 @@ | ||
| #define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3) | ||
| #define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8 | ||
| #define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50 | ||
| +#define LYNX_28G_LNaGCR0_PROTO_SEL_25G 0xD0 | ||
| #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0) | ||
| #define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT 0x0 | ||
| #define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT 0x2 | ||
| +#define LYNX_28G_LNaGCR0_IF_WIDTH_40_BIT 0x4 | ||
|
|
||
| /* Lane a Tx Reset Control Register */ | ||
| #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) | ||
| @@ -67,6 +75,7 @@ | ||
| #define LYNX_28G_LNaTGCR0_N_RATE_FULL 0x0 | ||
| #define LYNX_28G_LNaTGCR0_N_RATE_HALF 0x1000000 | ||
| #define LYNX_28G_LNaTGCR0_N_RATE_QUARTER 0x2000000 | ||
| +#define LYNX_28G_LNaTGCR0_N_RATE_DOUBLE 0x3000000 | ||
| #define LYNX_28G_LNaTGCR0_N_RATE_MSK GENMASK(26, 24) | ||
|
|
||
| #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) | ||
| @@ -87,6 +96,7 @@ | ||
| #define LYNX_28G_LNaRGCR0_N_RATE_FULL 0x0 | ||
| #define LYNX_28G_LNaRGCR0_N_RATE_HALF 0x1000000 | ||
| #define LYNX_28G_LNaRGCR0_N_RATE_QUARTER 0x2000000 | ||
| +#define LYNX_28G_LNaRGCR0_N_RATE_DOUBLE 0x3000000 | ||
| #define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24) | ||
|
|
||
| #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48) | ||
| @@ -95,12 +105,17 @@ | ||
| #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54) | ||
| #define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58) | ||
|
|
||
| +#define LYNX_28G_LNaRCCR0(lane) (0x800 + (lane) * 0x100 + 0x68) | ||
| + | ||
| #define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74) | ||
|
|
||
| +#define LYNX_28G_LNaTTLCR0(lane) (0x800 + (lane) * 0x100 + 0x80) | ||
| + | ||
| #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4) | ||
| #define LYNX_28G_LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24) | ||
| #define LYNX_28G_LNaPSS_TYPE_SGMII 0x4 | ||
| #define LYNX_28G_LNaPSS_TYPE_XFI 0x28 | ||
| +#define LYNX_28G_LNaPSS_TYPE_25G 0x68 | ||
|
|
||
| #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) | ||
| #define LYNX_28G_SGMIIaCR1_SGPCS_EN BIT(11) | ||
| @@ -216,6 +231,16 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane, | ||
| break; | ||
| } | ||
| break; | ||
| + case LYNX_28G_PLLnCR1_FRATE_12G_25GVCO: | ||
| + switch (intf) { | ||
| + case PHY_INTERFACE_MODE_25GBASER: | ||
| + lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_DOUBLE, N_RATE_MSK); | ||
| + lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_DOUBLE, N_RATE_MSK); | ||
| + break; | ||
| + default: | ||
| + break; | ||
| + } | ||
| + break; | ||
| default: | ||
| break; | ||
| } | ||
| @@ -235,21 +260,35 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane, | ||
|
|
||
| static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane) | ||
| { | ||
| - u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); | ||
| struct lynx_28g_priv *priv = lane->priv; | ||
| + u32 lane_offset; | ||
|
|
||
| - /* Cleanup the protocol configuration registers of the current protocol */ | ||
| switch (lane->interface) { | ||
| case PHY_INTERFACE_MODE_10GBASER: | ||
| + /* Cleanup the protocol configuration registers */ | ||
| + lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); | ||
| lynx_28g_rmw(priv, LYNX_28G_PCCC, | ||
| LYNX_28G_PCCC_SXGMII_DIS << lane_offset, | ||
| GENMASK(3, 0) << lane_offset); | ||
| break; | ||
| case PHY_INTERFACE_MODE_SGMII: | ||
| case PHY_INTERFACE_MODE_1000BASEX: | ||
| + /* Cleanup the protocol configuration registers */ | ||
| + lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); | ||
| lynx_28g_rmw(priv, LYNX_28G_PCC8, | ||
| LYNX_28G_PCC8_SGMII_DIS << lane_offset, | ||
| GENMASK(3, 0) << lane_offset); | ||
| + | ||
| + /* Disable the SGMII PCS */ | ||
| + lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK); | ||
| + | ||
| + break; | ||
| + case PHY_INTERFACE_MODE_25GBASER: | ||
| + /* Cleanup the protocol configuration registers */ | ||
| + lane_offset = LYNX_28G_LNa_PCCD_OFFSET(lane); | ||
| + lynx_28g_rmw(priv, LYNX_28G_PCCD, | ||
| + LYNX_28G_PCCD_25GBASER_DIS << lane_offset, | ||
| + GENMASK(2, 0) << lane_offset); | ||
| break; | ||
| default: | ||
| break; | ||
| @@ -316,9 +355,6 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) | ||
| /* Choose the portion of clock net to be used on this lane */ | ||
| lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER); | ||
|
|
||
| - /* Disable the SGMII PCS */ | ||
| - lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK); | ||
| - | ||
| /* Configure the appropriate equalization parameters for the protocol */ | ||
| iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id)); | ||
| iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); | ||
| @@ -330,6 +366,41 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) | ||
| iowrite32(0x00408000, priv->base + LYNX_28G_LNaTTLCR0(lane->id)); | ||
| } | ||
|
|
||
| +static void lynx_28g_lane_set_25gbaser(struct lynx_28g_lane *lane) | ||
| +{ | ||
| + u32 lane_offset = LYNX_28G_LNa_PCCD_OFFSET(lane); | ||
| + struct lynx_28g_priv *priv = lane->priv; | ||
| + struct lynx_28g_pll *pll; | ||
| + | ||
| + lynx_28g_cleanup_lane(lane); | ||
| + | ||
| + /* Enable the E25G lane */ | ||
| + lynx_28g_rmw(priv, LYNX_28G_PCCD, | ||
| + LYNX_28G_PCCD_25GBASER << lane_offset, | ||
| + GENMASK(2, 0) << lane_offset); | ||
| + | ||
| + /* Setup the protocol select and SerDes parallel interface width */ | ||
| + lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_25G, PROTO_SEL_MSK); | ||
| + lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_40_BIT, IF_WIDTH_MSK); | ||
| + | ||
| + /* Switch to the PLL that works with this interface type */ | ||
| + pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_25GBASER); | ||
| + lynx_28g_lane_set_pll(lane, pll); | ||
| + | ||
| + /* Choose the portion of clock net to be used on this lane */ | ||
| + lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_25GBASER); | ||
| + | ||
| + /* Configure the appropriate equalization parameters for 25GBASE-R */ | ||
| + iowrite32(0x20828700, priv->base + LYNX_28G_LNaTECR0(lane->id)); | ||
| + iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); | ||
| + iowrite32(0x00000085, priv->base + LYNX_28G_LNaRECR0(lane->id)); | ||
| + iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); | ||
| + iowrite32(0xa1000023, priv->base + LYNX_28G_LNaRECR2(lane->id)); | ||
| + iowrite32(0x00002020, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); | ||
| + iowrite32(0x8f000000, priv->base + LYNX_28G_LNaRCCR0(lane->id)); | ||
| + iowrite32(0x00008001, priv->base + LYNX_28G_LNaTTLCR0(lane->id)); | ||
| +} | ||
| + | ||
| static int lynx_28g_power_off(struct phy *phy) | ||
| { | ||
| struct lynx_28g_lane *lane = phy_get_drvdata(phy); | ||
| @@ -408,6 +479,9 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode) | ||
| case PHY_INTERFACE_MODE_10GBASER: | ||
| lynx_28g_lane_set_10gbaser(lane); | ||
| break; | ||
| + case PHY_INTERFACE_MODE_25GBASER: | ||
| + lynx_28g_lane_set_25gbaser(lane); | ||
| + break; | ||
| default: | ||
| err = -EOPNOTSUPP; | ||
| goto out; | ||
| @@ -492,8 +566,12 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv) | ||
| /* 10.3125GHz clock net */ | ||
| __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported); | ||
| break; | ||
| + case LYNX_28G_PLLnCR1_FRATE_12G_25GVCO: | ||
| + /* 12.890625GHz clock net */ | ||
| + __set_bit(PHY_INTERFACE_MODE_25GBASER, pll->supported); | ||
| + break; | ||
| default: | ||
| - /* 6GHz, 12.890625GHz, 8GHz */ | ||
| + /* 6GHz, 8GHz */ | ||
| break; | ||
| } | ||
| } | ||
| @@ -542,6 +620,9 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane) | ||
| case LYNX_28G_LNaPSS_TYPE_XFI: | ||
| lane->interface = PHY_INTERFACE_MODE_10GBASER; | ||
| break; | ||
| + case LYNX_28G_LNaPSS_TYPE_25G: | ||
| + lane->interface = PHY_INTERFACE_MODE_25GBASER; | ||
| + break; | ||
| default: | ||
| lane->interface = PHY_INTERFACE_MODE_NA; | ||
| } | ||
| -- | ||
| 2.43.0 | ||
|
|
53 changes: 53 additions & 0 deletions
53
patches/linux/0018-net-dpaa2-mac-add-25gbase-r-support.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,53 @@ | ||
| From 5d3fec396e8bfb535e4efbe120ef8206b4f5124d Mon Sep 17 00:00:00 2001 | ||
| From: Josua Mayer <[email protected]> | ||
| Date: Fri, 16 Jun 2023 14:14:14 +0300 | ||
| Subject: [PATCH 18/18] net: dpaa2-mac: add 25gbase-r support | ||
|
|
||
| Layerscape MACs support 25Gbps network speed with dpmac "CAUI" mode. | ||
| Add the mappings between DPMAC_ETH_IF_* and HY_INTERFACE_MODE_*, as well | ||
| as the 25000 mac capability. | ||
|
|
||
| Tested on SolidRun LX2162a Clearfog, serdes 1 protocol 18. | ||
|
|
||
| Signed-off-by: Josua Mayer <[email protected]> | ||
| Reviewed-by: Russell King (Oracle) <[email protected]> | ||
| Signed-off-by: David S. Miller <[email protected]> | ||
| --- | ||
| drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 7 ++++++- | ||
| 1 file changed, 6 insertions(+), 1 deletion(-) | ||
|
|
||
| diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | ||
| index ed4cac00fba6..55f08c84b3dc 100644 | ||
| --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | ||
| +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | ||
| @@ -55,6 +55,9 @@ static int phy_mode(enum dpmac_eth_if eth_if, phy_interface_t *if_mode) | ||
| case DPMAC_ETH_IF_XFI: | ||
| *if_mode = PHY_INTERFACE_MODE_10GBASER; | ||
| break; | ||
| + case DPMAC_ETH_IF_CAUI: | ||
| + *if_mode = PHY_INTERFACE_MODE_25GBASER; | ||
| + break; | ||
| default: | ||
| return -EINVAL; | ||
| } | ||
| @@ -80,6 +83,8 @@ static enum dpmac_eth_if dpmac_eth_if_mode(phy_interface_t if_mode) | ||
| return DPMAC_ETH_IF_XFI; | ||
| case PHY_INTERFACE_MODE_1000BASEX: | ||
| return DPMAC_ETH_IF_1000BASEX; | ||
| + case PHY_INTERFACE_MODE_25GBASER: | ||
| + return DPMAC_ETH_IF_CAUI; | ||
| default: | ||
| return DPMAC_ETH_IF_MII; | ||
| } | ||
| @@ -411,7 +416,7 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac) | ||
|
|
||
| mac->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | | ||
| MAC_10FD | MAC_100FD | MAC_1000FD | MAC_2500FD | MAC_5000FD | | ||
| - MAC_10000FD; | ||
| + MAC_10000FD | MAC_25000FD; | ||
|
|
||
| dpaa2_mac_set_supported_interfaces(mac); | ||
|
|
||
| -- | ||
| 2.43.0 | ||
|
|
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