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Support of the flash for SiWx917 #64
Support of the flash for SiWx917 #64
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#size-cells = <1>; | ||
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// NWP (Network Processor) partition (do not overwrite) | ||
nwp_firmware_partition: partition@0 { |
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Is this correct? The NWP sees the flash at a different address (in the 0x4xxx range), where it has a 1.8 MB image that the M4 can't access. As I understand it, the memory map as seen by the M4 actually does start at 0x08202000, not 0x08200000.
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I have not found proper reference for memory mapping.
If I understand right, the "917 reference manual" says the flash start at 0x08000000
(4.3.4 Address Mapping). The size NWP firmware (in fact the size of the .rps
file) is 1.6MB. So, it would probably makes sense to reserve 2MB and place the M4 firmware at 0x08200000
. However, isp_prepare.py
prefixes the firmware with 4096 bytes for the rps header (I believe it could be decreased). So, the firmware should be placed at 0x08201000
.
BTW, the datasheet says siwg917m111mgtba
has 8MB of flash.
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After an investigation, our thought are that the flash start at 0x08000000 and has a size of 8MB. The NWP firmware partition would reserved 2MB of flash memory from 0x8000000 to 0x8200000. The code partition will start at 0x8200000 and will have a size of 6MB (we reserved 8KB for rps header at the start). As we are in a common flash mode, we supposed to be able to write from 0x8000000 to 0x8800000 (and eventually deliberately write on the nwp firmware in case of a test) but what we see is that we can only write in flash from 0x8200200 to 0x8400000. (like we only have 4KB of flash memory. discussion is ongoing with SMalae to understand what happens on NWP side with WiseConnect.
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The important thing to realize is that in common flash mode, the NWP owns the flash. The M4 is a subordinate that is only allowed to use the subset the NWP gives it access to. This is opposite from all other Silabs devices, where the user-facing CPU is the owner of its memory.
dts/arm/silabs/siwg917.dtsi
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#address-cells = <1>; | ||
#size-cells = <1>; | ||
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flash0: flash@8200000 { |
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I wonder if this should actually be moved to the board dts, since the address of the flash changes depending on whether the board uses common (internal) flash or dual flash. For now, I see that the flash driver only supports common flash, so it doesn't really matter, though.
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I also believe the size of the flash depends of the part.
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From my point of view and what I see in the other .dts, start address of the flash will be in siwg917.dtsi and the size of the flash will be in the part specific siwg917m111mgtba.dtsi. We then declare flash partition in the board specific .dts.
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SiWx917 is unique in that the start address changes depending on common vs. dual flash mode -- the memory mapping of "M4 gets access to a slice of the flash owned by the NWP" (common flash) vs. "M4 has its own dedicated flash" (dual flash) is completely different. It's really weird, but it's how it works. And the choice of whether the second flash chip is added is a board-level decision.
dts/arm/silabs/siwg917.dtsi
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#address-cells = <1>; | ||
#size-cells = <1>; | ||
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||
flash0: flash@8200000 { |
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I also believe the size of the flash depends of the part.
#size-cells = <1>; | ||
|
||
// NWP (Network Processor) partition (do not overwrite) | ||
nwp_firmware_partition: partition@0 { |
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I have not found proper reference for memory mapping.
If I understand right, the "917 reference manual" says the flash start at 0x08000000
(4.3.4 Address Mapping). The size NWP firmware (in fact the size of the .rps
file) is 1.6MB. So, it would probably makes sense to reserve 2MB and place the M4 firmware at 0x08200000
. However, isp_prepare.py
prefixes the firmware with 4096 bytes for the rps header (I believe it could be decreased). So, the firmware should be placed at 0x08201000
.
BTW, the datasheet says siwg917m111mgtba
has 8MB of flash.
If the DT node chosen/zephyr,flash is defined, the reg address of this device is used as default value for FLASH_BASE_ADDRESS. Using this feature the user does not have to repeat the same information in Device Tree and in the configuration. Signed-off-by: Jérôme Pouiller <[email protected]>
The flash driver need to initialize NetWork coProcessor (NWP) without BLE or WiFi. In addition, if neither BLE or WiFi is selected, compiler complain cfg is not used. So slightly change the code to make de compiler happy. Signed-off-by: Jérôme Pouiller <[email protected]>
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Mostly fine.
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With the help of SMalae, a confluence page (https://confluence.silabs.com/pages/viewpage.action?spaceKey=EN&title=9117B0+Flash+Map#id-9117B0FlashMap-M4regioninCommonflash-8MBGreenInuse) and this AN (https://www.silabs.com/documents/public/application-notes/an1416-siwx917-soc-memory-map.pdf) , it is much clearer now for me. I understand the fact that the flash start address will change with the dual flash mode and then the flash start address must be declared in the board.dts file. For the moment, the only mode supported is "common" so as you said @asmellby, it will be okay. The support of the dual flash memory might be done in another PR ? |
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The memory mapping is still not accurate. However, I believe we can move on.
I may submit a new PR with the changes I have in mind but it is not a priority for now.
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Looks generally fine, but please fix the return value type of flash_siwx917_range_is_in_bounds()
Add flash driver for SiWx917. Co-authored-by: Martin Hoff <[email protected]> Signed-off-by: Jérôme Pouiller <[email protected]> Signed-off-by: Martin Hoff <[email protected]>
Simplify code usage. Signed-off-by: Jérôme Pouiller <[email protected]>
A specific section of the flash on the SiWx917 is reserved for the Network co-processor (nwp). This zone needs to be delimited in order to not overwrite it. We then need to use "code-partition" to provide Zephyr the application code flash location. Signed-off-by: Martin Hoff <[email protected]>
Allow CI to build tests concerning flash driver. Extra-arg in the twister command line (DTC_OVERLAY_FILE) allows to have the .overlay file in zephyr-silabs repository and not in the official zephyr repository. Co-authored-by: Martin Hoff <[email protected]> Signed-off-by: Jérôme Pouiller <[email protected]> Signed-off-by: Martin Hoff <[email protected]>
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Multiple commits :