soc: silabs: siwg917: Use PLL as core clock

Use existing CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC to configure PLL frequency. Signed-off-by: Aksel Skauge Mellbye <[email protected]>
SiliconLabsSoftware · Aug 9, 2024 · 25ec2db · 25ec2db
1 parent 33432c8
commit 25ec2db
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diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Antmicro
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y

diff --git a/soc/silabs/silabs_siwx917/siwg917/soc.c b/soc/silabs/silabs_siwx917/siwg917/soc.c
@@ -9,11 +9,22 @@
 #include "rsi_rom_clks.h"
 #include "rsi_rom_ulpss_clk.h"
 
+#include "sl_si91x_clock_manager.h"
+
 int silabs_siwx917_init(void)
 {
 	SystemInit();
 	SystemCoreClockUpdate();
 
+	/* Use SoC PLL at configured frequency as core clock */
+	sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK,
+					       CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
+
+	/* Use interface PLL at configured frequency as peripheral clock */
+	sl_si91x_clock_manager_set_pll_freq(INFT_PLL,
+					    CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
+					    PLL_REF_CLK_VAL_XTAL);
+
 	/* FIXME: do not hardcode UART instances */
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpuart0), okay)
 	RSI_ULPSS_UlpUartClkConfig(ULPCLK, ENABLE_STATIC_CLK, 0, ULP_UART_ULP_32MHZ_RC_CLK, 1);