Tags: Seschlim/u-boot-socfpga
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HSD #22011135953-5: arm: socfpga: Enhance checking on potential overw… …rite Each register 4 bytes write, there is a potential that user setting an invalid offset which is less than block size, but overflow the block size when writing the register. This patch prevents this overwrite issue by checking earlier before starting any register write. Signed-off-by: Tien Fong Chee <[email protected]>
ddr: altera: n5x: Fixing debug log typo Fixing debug log typo. Signed-off-by: Tien Fong Chee <[email protected]>
drivers: fpga: intel_pr: enable illegal request detection This is to enable check on the freeze_illegal_request register whereby high on any bit of this bus indicates a read or write issue by a static region master when an freeze bridge is in the freeze state. In the case if any of the bit is high, write 1 to first clear the bit and then return with error. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@@intel.com>
Revert "fpga: intel_pr: enable illegal request detection" This reverts commit e5adc69. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@@intel.com>
Revert "fpga: intel_pr: enable illegal request detection" This reverts commit e5adc69. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@@intel.com>
Revert "fpga: intel_pr: enable illegal request detection" This reverts commit e5adc69. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@@intel.com>
HSD #14014209193: rsu: allow requesting any slot Allow rsu to request any slot to be loaded, not only slots which are included in the cpb. Signed-off-by: Radu Bacrau <[email protected]>
HSD #1508949110: set/clear reset_req bit before/after PR For Agilex and Stratix10, before FPGA Partial Reconfiguration (PR) operation, SW need to set reset_req bit in freeze_csr_ctrl register to reset PR region. The same bit need to be cleared after FPGA PR operation is done. Signed-off-by: Chew, Chiau Ee <[email protected]>
arm: socfpga: n5x: Replace with soc64 env settings Only DDR and clock changes in N5X compare with existing SOC64 devices, so a common SOC64 env setting can be used in N5X. Signed-off-by: Tien Fong Chee <[email protected]>
arm: socfpga: n5x: Replace with soc64 env settings Only DDR and clock changes in N5X compare with existing SOC64 devices, so a common SOC64 env setting can be used in N5X. Signed-off-by: Tien Fong Chee <[email protected]>
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