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Jit: Threads: Add simple RMW operations
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Does not include RmwCmpxchg

Signed-off-by: Máté Tokodi [email protected]
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@matetokodi
matetokodi committed Jul 26, 2024
1 parent 69fd93a commit d4eb1a6
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Showing 4 changed files with 413 additions and 0 deletions.
6 changes: 6 additions & 0 deletions src/jit/Backend.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1238,6 +1238,12 @@ void JITCompiler::compileFunction(JITFunction* jitFunc, bool isExternal)
emitStackInit(m_compiler, item->asInstruction());
break;
}
#if defined(ENABLE_EXTENDED_FEATURES)
case Instruction::Atomic: {
emitAtomic(m_compiler, item->asInstruction());
break;
}
#endif /* ENABLE_EXTENDED_FEATURES */
default: {
switch (item->asInstruction()->opcode()) {
case ByteCode::SelectOpcode: {
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84 changes: 84 additions & 0 deletions src/jit/ByteCodeParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -230,6 +230,14 @@ static bool isFloatGlobal(uint32_t globalIndex, Module* module)

#endif /* SLJIT_32BIT_ARCHITECTURE */

#if defined(ENABLE_EXTENDED_FEATURES)
#define OPERAND_TYPE_LIST_ATOMIC \
OL6(OTAtomicRmwI32, /* SSDTTT */ I32, I32, I32, PTR, I32 | S0, PTR | S1) \
OL6(OTAtomicRmwI64, /* SSDTTT */ I32, I64, I64, PTR, I64 | S0, I64 | S1)
#else /* !ENABLE_EXTENDED_FEATURES */
#define OPERAND_TYPE_LIST_ATOMIC
#endif /* ENABLE_EXTENDED_FEATURES */

#define OPERAND_TYPE_LIST_SIMD \
OL2(OTOp1V128, /* SD */ V128 | NOTMP, V128 | TMP | S0) \
OL2(OTOpCondV128, /* SD */ V128 | TMP, I32) \
Expand Down Expand Up @@ -319,18 +327,22 @@ static bool isFloatGlobal(uint32_t globalIndex, Module* module)
o1, o2, o3, o4, 0,
#define OL5(name, o1, o2, o3, o4, o5) \
o1, o2, o3, o4, o5, 0,
#define OL6(name, o1, o2, o3, o4, o5, o6) \
o1, o2, o3, o4, o5, o6, 0,

const uint8_t Instruction::m_operandDescriptors[] = {
0,
OPERAND_TYPE_LIST OPERAND_TYPE_LIST_MATH
OPERAND_TYPE_LIST_SIMD OPERAND_TYPE_LIST_SIMD_ARCH
OPERAND_TYPE_LIST_ATOMIC
};

#undef OL1
#undef OL2
#undef OL3
#undef OL4
#undef OL5
#undef OL6

// Besides the list names, these macros define enum
// types with ByteN suffix. These are unused.
Expand All @@ -345,20 +357,24 @@ const uint8_t Instruction::m_operandDescriptors[] = {
name, name##Byte1, name##Byte2, name##Byte3, name##Byte4,
#define OL5(name, o1, o2, o3, o4, o5) \
name, name##Byte1, name##Byte2, name##Byte3, name##Byte4, name##Byte5,
#define OL6(name, o1, o2, o3, o4, o5, o6) \
name, name##Byte1, name##Byte2, name##Byte3, name##Byte4, name##Byte5, name##Byte6,

enum OperandTypes : uint32_t {
OTNone,
OPERAND_TYPE_LIST
OPERAND_TYPE_LIST_MATH
OPERAND_TYPE_LIST_SIMD
OPERAND_TYPE_LIST_SIMD_ARCH
OPERAND_TYPE_LIST_ATOMIC
};

#undef OL1
#undef OL2
#undef OL3
#undef OL4
#undef OL5
#undef OL6

enum ParamTypes {
NoParam,
Expand Down Expand Up @@ -1898,6 +1914,74 @@ static void compileFunction(JITCompiler* compiler)
operands[1] = STACK_OFFSET(atomicStore->src1Offset());
break;
}
case ByteCode::I32AtomicRmwAddOpcode:
case ByteCode::I32AtomicRmw8AddUOpcode:
case ByteCode::I32AtomicRmw16AddUOpcode:
case ByteCode::I32AtomicRmwSubOpcode:
case ByteCode::I32AtomicRmw8SubUOpcode:
case ByteCode::I32AtomicRmw16SubUOpcode:
case ByteCode::I32AtomicRmwAndOpcode:
case ByteCode::I32AtomicRmw8AndUOpcode:
case ByteCode::I32AtomicRmw16AndUOpcode:
case ByteCode::I32AtomicRmwOrOpcode:
case ByteCode::I32AtomicRmw8OrUOpcode:
case ByteCode::I32AtomicRmw16OrUOpcode:
case ByteCode::I32AtomicRmwXorOpcode:
case ByteCode::I32AtomicRmw8XorUOpcode:
case ByteCode::I32AtomicRmw16XorUOpcode:
case ByteCode::I32AtomicRmwXchgOpcode:
case ByteCode::I32AtomicRmw8XchgUOpcode:
case ByteCode::I32AtomicRmw16XchgUOpcode: {
info = Instruction::kIs32Bit;
requiredInit = OTAtomicRmwI32;
FALLTHROUGH;
}
case ByteCode::I64AtomicRmwAddOpcode:
case ByteCode::I64AtomicRmw8AddUOpcode:
case ByteCode::I64AtomicRmw16AddUOpcode:
case ByteCode::I64AtomicRmw32AddUOpcode:
case ByteCode::I64AtomicRmwSubOpcode:
case ByteCode::I64AtomicRmw8SubUOpcode:
case ByteCode::I64AtomicRmw16SubUOpcode:
case ByteCode::I64AtomicRmw32SubUOpcode:
case ByteCode::I64AtomicRmwAndOpcode:
case ByteCode::I64AtomicRmw8AndUOpcode:
case ByteCode::I64AtomicRmw16AndUOpcode:
case ByteCode::I64AtomicRmw32AndUOpcode:
case ByteCode::I64AtomicRmwOrOpcode:
case ByteCode::I64AtomicRmw8OrUOpcode:
case ByteCode::I64AtomicRmw16OrUOpcode:
case ByteCode::I64AtomicRmw32OrUOpcode:
case ByteCode::I64AtomicRmwXorOpcode:
case ByteCode::I64AtomicRmw8XorUOpcode:
case ByteCode::I64AtomicRmw16XorUOpcode:
case ByteCode::I64AtomicRmw32XorUOpcode:
case ByteCode::I64AtomicRmwXchgOpcode:
case ByteCode::I64AtomicRmw8XchgUOpcode:
case ByteCode::I64AtomicRmw16XchgUOpcode:
case ByteCode::I64AtomicRmw32XchgUOpcode: {
Instruction* instr = compiler->append(byteCode, Instruction::Atomic, opcode, 2, 1);
#if (defined SLJIT_32BIT_ARCHITECTURE && SLJIT_32BIT_ARCHITECTURE)
if (opcode == ByteCode::I64AtomicRmwAddOpcode
|| opcode == ByteCode::I64AtomicRmwSubOpcode
|| opcode == ByteCode::I64AtomicRmwAndOpcode
|| opcode == ByteCode::I64AtomicRmwOrOpcode
|| opcode == ByteCode::I64AtomicRmwXorOpcode
|| opcode == ByteCode::I64AtomicRmwXchgOpcode) {
info = Instruction::kIsCallback;
}
#endif /* SLJIT_32BIT_ARCHITECTURE */
instr->addInfo(info);

AtomicRmw* atomicRmw = reinterpret_cast<AtomicRmw*>(byteCode);
Operand* operands = instr->operands();
instr->setRequiredRegsDescriptor(requiredInit != OTNone ? requiredInit : OTAtomicRmwI64);

operands[0] = STACK_OFFSET(atomicRmw->src0Offset());
operands[1] = STACK_OFFSET(atomicRmw->src1Offset());
operands[2] = STACK_OFFSET(atomicRmw->dstOffset());
break;
}
#endif /* ENABLE_EXTENDED_FEATURES */
default: {
ASSERT_NOT_REACHED();
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4 changes: 4 additions & 0 deletions src/jit/Compiler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,10 @@ class InstructionListItem {
ShiftSIMD,
// Special type for initializing values from the stack
StackInit,
#if defined(ENABLE_EXTENDED_FEATURES)
// Atomic memory operations (e.g. I32AtomicRmwAdd, I64AtomicRmw16OrU)
Atomic,
#endif /* ENABLE_EXTENDED_FEATURES */
};

virtual ~InstructionListItem() {}
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