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Some more clock enabling
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SagarDevAchar authored Sep 1, 2024
1 parent bd35834 commit f4c0529
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Showing 5 changed files with 6,605 additions and 6,969 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/docs.yaml
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@@ -1,7 +1,7 @@
name: docs

on:
# push:
push:
workflow_dispatch:

jobs:
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2 changes: 1 addition & 1 deletion .github/workflows/gds.yaml
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@@ -1,7 +1,7 @@
name: gds

on:
# push:
push:
workflow_dispatch:

jobs:
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7 changes: 5 additions & 2 deletions docs/info.md
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Expand Up @@ -13,8 +13,11 @@ It just works!

## How to test

Just provide clock and reset
- Connect the necessary peripherals
- Provide a 25MHz clock
- Reset the design

## External hardware

VGA and Audio PMOD
- Tiny VGA Pmod connected to output terminal (`uo_out`)
- TT Audio Pmod connected to inout terminal (`uio_out`)
20 changes: 16 additions & 4 deletions src/graphics_engine.v
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Expand Up @@ -16,11 +16,23 @@ module graphics_engine(
reg [9:0] ctr;
wire [9:0] anim_x, anim_2x;

always @(posedge v_sync, negedge rst_n) begin
if (~rst_n)
reg en_v_sync;
always @(posedge clk, negedge rst_n) begin
if (~rst_n )begin
ctr <= 10'd0;
else
ctr <= ctr + 1'd1;
en_v_sync <= 1'b1;
end else begin
if (en_v_sync) begin
if (v_sync) begin
en_v_sync <= 1'b0;
ctr <= ctr + 1'd1;
end
end else begin
if (~v_sync)
en_v_sync <= 1'b1;
end
end

end

assign anim_x = x + ctr;
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