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Inducing errors
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@SagarDevAchar
SagarDevAchar authored Aug 26, 2024
1 parent 5f605e0 commit 9e5a608
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2 changes: 1 addition & 1 deletion test/Makefile
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SIM ?= icarus
TOPLEVEL_LANG ?= verilog
SRC_DIR = $(PWD)/../src
PROJECT_SOURCES = $(wildcard *.v)
PROJECT_SOURCES = x.v


ifneq ($(GATES),yes)
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