Test preparedness and remove driven constant

src/project.v

@@ -49,8 +49,6 @@ module tt_um_demosiine_sda (
     };
     assign uio_out = {audio, 7'd0};
     assign uio_oe  = 8'b1000_0000;
-
-    assign {r, g, b} = 6'b11_11_11;
 
     // TODO: Unused
     // wire _unused = &{ena, ui_in, uio_in, x, y, frame_active};

test/tb.v

@@ -24,7 +24,7 @@ module tb ();
   wire [7:0] uio_oe;
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_demosiine_sda (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST

test/test.py

@@ -10,8 +10,8 @@
 async def test_project(dut):
     dut._log.info("Start")
 
-    # Set the clock period to 10 us (100 KHz)
-    clock = Clock(dut.clk, 10, units="us")
+    # Set the clock period to 40 ns (25 MHz)
+    clock = Clock(dut.clk, 40, units="ns")
     cocotb.start_soon(clock.start())
 
     # Reset
@@ -26,15 +26,17 @@ async def test_project(dut):
     dut._log.info("Test project behavior")
 
     # Set the input values you want to test
-    dut.ui_in.value = 20
-    dut.uio_in.value = 30
+    # dut.ui_in.value = 20
+    # dut.uio_in.value = 30
+    # TODO
 
     # Wait for one clock cycle to see the output values
-    await ClockCycles(dut.clk, 1)
+    # await ClockCycles(dut.clk, 1)
 
     # The following assersion is just an example of how to check the output values.
     # Change it to match the actual expected output of your module:
-    assert dut.uo_out.value == 50
+    # assert dut.uo_out.value == 50
+    # TODO
 
     # Keep testing the module by changing the input values, waiting for
     # one or more clock cycles, and asserting the expected output values.