Trying to pass PROC_DFF

src/freq_synth.v

@@ -10,7 +10,7 @@ module freq_synth(
     reg audio_reg;
     reg [6:0] hp_ctr;
     always @(posedge synth_clk, negedge rst_n) begin
-        if (~active | ~rst_n) begin
+        if (~rst_n) begin
             audio_reg <= 1'd0;  
             hp_ctr <= 7'd1;
         end else begin