Skip to content

Commit

Permalink
Full integration
Browse files Browse the repository at this point in the history
  • Loading branch information
@SagarDevAchar
SagarDevAchar authored Aug 26, 2024
1 parent 178ecda commit 3cc3fa3
Show file tree
Hide file tree
Showing 10 changed files with 423 additions and 6 deletions.
6 changes: 6 additions & 0 deletions info.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,12 @@ project:
source_files:
- "project.v"
- "vga_controller.v"
- "graphics_engine.v"
- "overlay_creator.v"
- "text_demosiine.v"
- "text_tt08.v"
- "text_sda.v"
- "sine_layer.v"
- "audio_engine.v"
- "freq_synth.v"

Expand Down
3 changes: 2 additions & 1 deletion src/audio_engine.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -130,5 +130,6 @@ module audio_engine(
.active(seq_active)
);

wire _unused = 0;
// TODO: Unused
// wire _unused = 0;
endmodule
3 changes: 2 additions & 1 deletion src/freq_synth.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,5 +24,6 @@ module freq_synth(

assign audio = audio_reg & active;

wire _unused = 0;
// TODO: Unused
// wire _unused = 0;
endmodule
69 changes: 69 additions & 0 deletions src/graphics_engine.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,69 @@
`default_nettype none

module graphics_engine(
output wire [1:0] r, g, b,
input wire [9:0] x, y,
input wire frame_active, v_sync,
input wire clk, rst_n
);

wire [5:0] sine_off_y, sine_bg_off_y;

wire [5:0] overlay_rgb, sine_rgb, sine_bg_rgb, sine_rgb_dither, sine_bg_rgb_dither;
wire overlay_active, overlay_text_active, sine_active, sine_bg_active;

reg [9:0] ctr;
wire [9:0] anim_x, anim_2x;

always @ (posedge v_sync) begin
if (~rst_n)
ctr <= 0;
else
ctr <= ctr + 1;
end

assign anim_x = x + ctr;
assign anim_2x = x + {ctr[8:0], 1'd0};

overlay_creator overlay_creator1 (
.overlay_active(overlay_active), .text_active(overlay_text_active),
.x(x), .y(y),
.clk(clk), .rst_n(rst_n)
);

assign sine_off_y = y[9:4] - 5'd3;
assign sine_bg_off_y = y[8:3] - 5'd2;

sine_layer sine_layer1 (
.sine_rgb(sine_rgb),
.x(anim_x[8:3]),
.y(sine_off_y[4:0])
);

sine_layer sine_layer2 (
.sine_rgb(sine_bg_rgb),
.x(anim_2x[7:2]),
.y(sine_bg_off_y[4:0])
);

assign overlay_rgb = overlay_active ? {
{overlay_text_active, ctr[7], overlay_text_active, ctr[6], overlay_text_active, ctr[5]}
} : 6'b00_00_00;

assign sine_rgb_dither = sine_rgb & {6{(x[0] ^ y[0])}};
assign sine_bg_rgb_dither = sine_bg_rgb & {6{(x[0] & y[0])}};

assign sine_active = |sine_rgb_dither;
assign sine_bg_active = |sine_bg_rgb_dither;

assign {r, g, b} = frame_active ? (
overlay_active ? overlay_rgb : (
sine_active ? sine_rgb_dither : (
sine_bg_active ? sine_bg_rgb_dither : 6'b00_00_00
)
)
) : 6'b00_00_00;

// TODO: Unused
// wire _unused = &{x[7:0], y[7:0], rst_n, v_sync};
endmodule
57 changes: 57 additions & 0 deletions src/overlay_creator.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,57 @@
`default_nettype none

module overlay_creator(
output wire overlay_active, text_active,
input wire [9:0] x, y
);

//TODO: Double Layer optimization

wire [9:0] x_shadow, y_shadow;
wire shadow_active;

wire text_demosiine_main_active, text_demosiine_shadow_active;
wire text_tt08_main_active, text_tt08_shadow_active;
wire text_sda_main_active, text_sda_shadow_active;

assign x_shadow = x - 10'd4;
assign y_shadow = y - 10'd4;

text_demosiine text_demosiine1 (
.overlay_active(text_demosiine_main_active),
.x(x), .y(y)
);

text_demosiine text_demosiine2 (
.overlay_active(text_demosiine_shadow_active),
.x(x_shadow), .y(y_shadow)
);

text_tt08 text_tt081 (
.overlay_active(text_tt08_main_active),
.x(x), .y(y)
);

text_tt08 text_tt082 (
.overlay_active(text_tt08_shadow_active),
.x(x_shadow), .y(y_shadow)
);

text_sda text_sda1 (
.overlay_active(text_sda_main_active),
.x(x), .y(y)
);

text_sda text_sda2 (
.overlay_active(text_sda_shadow_active),
.x(x_shadow), .y(y_shadow)
);

assign text_active = text_demosiine_main_active | text_tt08_main_active | text_sda_main_active;
assign shadow_active = text_demosiine_shadow_active | text_tt08_shadow_active | text_sda_shadow_active;

assign overlay_active = text_active | shadow_active;

// TODO: Unused
// wire _unused = 0;
endmodule
8 changes: 4 additions & 4 deletions src/project.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,12 +30,12 @@ module tt_um_demosiine_sda (
.clk(clk), .rst_n(rst_n)
);

/*graphics_engine graphics_engine_1 (
graphics_engine graphics_engine_1 (
.r(r), .g(g), .b(b),
.x(x), .y(y),
.frame_active(frame_active), .v_sync(v_sync),
.clk(clk), .rst_n(rst_n)
);*/
);

audio_engine audio_engine_1 (
.audio(audio),
Expand All @@ -52,7 +52,7 @@ module tt_um_demosiine_sda (

assign {r, g, b} = 6'b11_11_11;

// List all unused inputs to prevent warnings
wire _unused = &{ena, ui_in, uio_in, x, y, frame_active};
// TODO: Unused
// wire _unused = &{ena, ui_in, uio_in, x, y, frame_active};

endmodule
145 changes: 145 additions & 0 deletions src/sine_layer.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,145 @@
`default_nettype none

module sine_layer (
output reg [5:0] sine_rgb,
input wire [5:0] x,
input wire [4:0] y
);

localparam [15:0] qsine_line00 = 16'b1100000000000000;
localparam [15:0] qsine_line01 = 16'b0011100000000000;
localparam [15:0] qsine_line02 = 16'b0000011000000000;
localparam [15:0] qsine_line03 = 16'b0000000110000000;
localparam [15:0] qsine_line04 = 16'b0000000001000000;
localparam [15:0] qsine_line05 = 16'b0000000000100000;
localparam [15:0] qsine_line06 = 16'b0000000000010000;
localparam [15:0] qsine_line07 = 16'b0000000000001000;
localparam [15:0] qsine_line08 = 16'b0000000000000100;
localparam [15:0] qsine_line09 = 16'b0000000000000010;
localparam [15:0] qsine_line10 = 16'b0000000000000001;

function [3:0] sub_floor(input [3:0] a, b);
sub_floor = (a < b) ? 4'd0 : (a - b);
endfunction

function automatic [3:0] add_ceil(input [3:0] a, b);
reg [3:0] t;
begin
t = a + b;
add_ceil = (a[3] ? (t[3] ? t : 4'd15) : t);
end
endfunction

wire [5:0] qsine_off_x, qsine_flip_x;
wire [4:0] qsine_off_y, qsine_flip_y;

wire [4:0] qsine_line_index;

function [5:0] qsine_colour(input [15:0] line, input inverted);
begin
if (inverted) begin
if (qsine_off_x[4])
qsine_colour = 6'b00_00_00;
else begin
if (qsine_off_x[3])
qsine_colour = 6'b00_00_00;
else begin
if (line[qsine_flip_x[3:0] + 4'd1])
qsine_colour = 6'b11_00_00;
else if (line[qsine_flip_x[3:0] + 4'd2])
qsine_colour = 6'b11_10_00;
else if (line[qsine_flip_x[3:0] + 4'd3])
qsine_colour = 6'b11_11_00;
else if (line[qsine_flip_x[3:0] + 4'd4])
qsine_colour = 6'b00_11_00;
else if (line[qsine_flip_x[3:0] + 4'd5])
qsine_colour = 6'b00_10_11;
else if (line[qsine_flip_x[3:0] + 4'd6])
qsine_colour = 6'b00_00_11;
else if (line[qsine_flip_x[3:0] + 4'd7])
qsine_colour = 6'b10_00_11;
else
qsine_colour = 6'b00_00_00;
end
end
end else begin
if (qsine_off_x[4]) begin
if (line[qsine_flip_x[3:0]])
qsine_colour = 6'b11_11_11;
else if (line[add_ceil(qsine_flip_x[3:0], 4'd1)])
qsine_colour = 6'b11_00_00;
else if (line[add_ceil(qsine_flip_x[3:0], 4'd2)])
qsine_colour = 6'b11_10_00;
else if (line[add_ceil(qsine_flip_x[3:0], 4'd3)])
qsine_colour = 6'b11_11_00;
else if (line[add_ceil(qsine_flip_x[3:0], 4'd4)])
qsine_colour = 6'b00_11_00;
else if (line[add_ceil(qsine_flip_x[3:0], 4'd5)])
qsine_colour = 6'b00_10_11;
else if (line[add_ceil(qsine_flip_x[3:0], 4'd6)])
qsine_colour = 6'b00_00_11;
else if (line[add_ceil(qsine_flip_x[3:0], 4'd7)])
qsine_colour = 6'b10_00_11;
else
qsine_colour = 6'b00_00_00;
end else begin
if (line[qsine_off_x[3:0]])
qsine_colour = 6'b11_11_11;
else if (line[sub_floor(qsine_off_x[3:0], 4'd1)])
qsine_colour = 6'b11_00_00;
else if (line[sub_floor(qsine_off_x[3:0], 4'd2)])
qsine_colour = 6'b11_10_00;
else if (line[sub_floor(qsine_off_x[3:0], 4'd3)])
qsine_colour = 6'b11_11_00;
else if (line[sub_floor(qsine_off_x[3:0], 4'd4)])
qsine_colour = 6'b00_11_00;
else if (line[sub_floor(qsine_off_x[3:0], 4'd5)])
qsine_colour = 6'b00_10_11;
else if (line[sub_floor(qsine_off_x[3:0], 4'd6)])
qsine_colour = 6'b00_00_11;
else if (line[sub_floor(qsine_off_x[3:0], 4'd7)])
qsine_colour = 6'b10_00_11;
else
qsine_colour = 6'b00_00_00;
end
end
end
endfunction

assign qsine_off_x = x;
assign qsine_off_y = y;

assign qsine_flip_x = 6'd31 - qsine_off_x;
assign qsine_flip_y = 5'd21 - qsine_off_y;

assign qsine_line_index = qsine_off_x[5] ? qsine_flip_y : qsine_off_y;

always @(*) begin
case (qsine_line_index)
5'h00: sine_rgb = qsine_colour(qsine_line00, 1'd0);
5'h01: sine_rgb = qsine_colour(qsine_line01, 1'd0);
5'h02: sine_rgb = qsine_colour(qsine_line02, 1'd0);
5'h03: sine_rgb = qsine_colour(qsine_line03, 1'd0);
5'h04: sine_rgb = qsine_colour(qsine_line04, 1'd0);
5'h05: sine_rgb = qsine_colour(qsine_line05, 1'd0);
5'h06: sine_rgb = qsine_colour(qsine_line06, 1'd0);
5'h07: sine_rgb = qsine_colour(qsine_line07, 1'd0);
5'h08: sine_rgb = qsine_colour(qsine_line08, 1'd0);
5'h09: sine_rgb = qsine_colour(qsine_line09, 1'd0);
5'h0A: sine_rgb = qsine_colour(qsine_line10, 1'd0);

5'h0B: sine_rgb = qsine_colour(qsine_line10, 1'd1);
5'h0C: sine_rgb = qsine_colour(qsine_line09, 1'd1);
5'h0D: sine_rgb = qsine_colour(qsine_line08, 1'd1);
5'h0E: sine_rgb = qsine_colour(qsine_line07, 1'd1);
5'h0F: sine_rgb = qsine_colour(qsine_line06, 1'd1);
5'h10: sine_rgb = qsine_colour(qsine_line05, 1'd1);
5'h11: sine_rgb = qsine_colour(qsine_line04, 1'd1);
5'h12: sine_rgb = qsine_colour(qsine_line03, 1'd1);
default: sine_rgb = 6'b00_00_00;
endcase
end

// TODO: Unused
// wire _unused = &{qsine_flip_x[5:4]};
endmodule
46 changes: 46 additions & 0 deletions src/text_demosiine.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
`default_nettype none

module text_demosiine(
output wire overlay_active,
input wire [9:0] x, y
);

// TODO: Try array-based optimization
parameter [45:0] demosiine_line0 = 46'b0000000000000000001110000000000000000000001111;
parameter [45:0] demosiine_line1 = 46'b0000000000000000000001000000000000000000010001;
parameter [45:0] demosiine_line2 = 46'b0000000000000000000000100000000000000000100001;
parameter [45:0] demosiine_line3 = 46'b0000000000000000000000100000000000000000100001;
parameter [45:0] demosiine_line4 = 46'b1111010010111011100111000110010001011110100001;
parameter [45:0] demosiine_line5 = 46'b0001010110010001001000001001011011000010100001;
parameter [45:0] demosiine_line6 = 46'b0111011010010001001000001001010101001110100001;
parameter [45:0] demosiine_line7 = 46'b0001010010010001000100001001010001000010010001;
parameter [45:0] demosiine_line8 = 46'b1111010010111011100011100110010001011110001111;

wire [6:0] demosiine_off_x;
wire [5:0] demosiine_off_y;

reg demosiine_active;

assign demosiine_off_x = x[9:3] - 7'd18;
assign demosiine_off_y = y[8:3] - 6'd12;

always @(*) begin
case (demosiine_off_y)
6'd0: demosiine_active = demosiine_line0[demosiine_off_x];
6'd1: demosiine_active = demosiine_line1[demosiine_off_x];
6'd2: demosiine_active = demosiine_line2[demosiine_off_x];
6'd3: demosiine_active = demosiine_line3[demosiine_off_x];
6'd4: demosiine_active = demosiine_line4[demosiine_off_x];
6'd5: demosiine_active = demosiine_line5[demosiine_off_x];
6'd6: demosiine_active = demosiine_line6[demosiine_off_x];
6'd7: demosiine_active = demosiine_line7[demosiine_off_x];
6'd8: demosiine_active = demosiine_line8[demosiine_off_x];
default: demosiine_active = 0;
endcase
end

assign overlay_active = (demosiine_off_x < 7'd47) & demosiine_active;

// TODO: Unused
// wire _unused = 0;
endmodule
Loading

0 comments on commit 3cc3fa3

Please sign in to comment.