Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation
This is one of the course project materials for HKUST-GZ MICS 6000H Logic Design Automation of Digital Systems. This project is alive, maintained by [email protected]. Any discussion or suggestion would be greatly appreciated!
- Python 3.9
- ply 3.11
- graphviz 0.20.1
- logging 0.5.1.2
- pyeda 0.28.0
- Vivado 2020.2
- GUI is not required. Only using the standalone simulation commands. Details shown in runsim.sh
xvlog
xelab
xsim
- GUI is not required. Only using the standalone simulation commands. Details shown in runsim.sh
- Front-end:
- lex (lexer)
- yacc (parser)
- Middle-end
- 2-level AND/OR logic minimization with ESPRESSO (with pyeda package)
- NAND/NOR minimization
- Back-end
- Verilog code generation
- testbench generation
- Step 0:
./clean.sh
- Clean all cached files, and make sure the tool is not using outdated intermediate results. (Although our tool would overwrite intermediate files in most cases, this is a safer choice.)
- Step 1: Make sure you have a valid Verilog expression in test.v
- We currently only support the following operators
- BITWISE_AND:
"&"
: bitwise AND (binary) / reduction AND (unary) - BITWISE_OR:
"|"
: bitwise OR (binary) / reduction OR (unary) - BITWISE_NEG:
"~"
: bitwise NEG (unary) [returns the complement of a variable] - LOGICAL_AND:
"&&"
: logical AND (binary) - LOGICAL_OR:
"||"
: logical OR (binary) - LOGICAL_NEG:
"!"
: logical NEG (unary) [returns a single bit]
- BITWISE_AND:
- We currently only support the following operators
- Step 2:
python main.py test.v
- This step generates the following files, including NAND/NOR implementation and the testbench.
- func.v: self-defined format -- "NAND g0(in1, in2, out);"
- func_vivado.v: format accepted by Vivado simulation tools -- "nand g0(out, in1, in2);"
- sim_func.v: testbench, end-to-end exhaustive comparison between (1) the NAND/NOR impl and (2) the original Verilog expr.
- This step generates the following files, including NAND/NOR implementation and the testbench.
- Step 3:
./runsim.sh
- This step triggers the simulation flow and gives standard output in the terminal.
- We here provide some examples of Boolean expressions for test. You can write any expression as long as the operators are supported, and paste into test.v, then
python main.py test.v
to run the program.~(!a | b)
b | (b&c)
a | !a & b
~(a&b)
!(c || d)
a&b&c | (a&b&!d) | (a&b&~e)
a & ~a
a || ~a
a & (b || ~b)
~a & (b || ~b)
A & B & C
A | B | C
a|||b
~a & ~b & ~c | ~a & ~b & c | a & ~b & c | a & b & c | a & b & ~c
(!a || (a && b) || (a && c) || (b && !c)) && ~b | | 1'h0 & &c
~a & b & c | ~d | ~b & d | a & d & c
- NAND logic:
~
/!
: NOT(A) -> A NAND A&
/&&
: A AND B -> (A NAND B) NAND (A NAND B)|
/||
: A OR B -> (A NAND A) NAND (B NAND B)&
/|
(reduction)-> A [itself]
- NOR logic:
~
/!
: NOT(A) -> A NOR A&
/&&
: A AND B -> (A NOR A) NOR (B NOR B)|
/||
: A OR B -> (A NOR B) NOR (A NOR B)&
/|
(reduction)-> A [itself]
- Documents:
- Blogs:
- Webpages Intros:
- Slides:
- GitHub links:
- Online tools: