Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
ALU_LEGv8.v		ALU_LEGv8.v
ALU_testbench.v		ALU_testbench.v
CLA_16bit.v		CLA_16bit.v
CLA_4bit.v		CLA_4bit.v
CLA_64bit.v		CLA_64bit.v
CLA_testbench.v		CLA_testbench.v
Control_Unit.v		Control_Unit.v
Control_unit_TestBench.v		Control_unit_TestBench.v
DatapathLEGv8.v		DatapathLEGv8.v
Datapath_testbench.v		Datapath_testbench.v
Decoder5to32.v		Decoder5to32.v
GPIO_Board.v		GPIO_Board.v
GPIO_Peripheral.v		GPIO_Peripheral.v
LEGv8_DE0.v		LEGv8_DE0.v
LEGv8_core.v		LEGv8_core.v
Mux2to1Nbit.v		Mux2to1Nbit.v
Mux32to1Nbit.v		Mux32to1Nbit.v
Mux4to1nbit.v		Mux4to1nbit.v
Muxes.v		Muxes.v
PC.v		PC.v
PC_out_testbench.v		PC_out_testbench.v
RAM256x64.v		RAM256x64.v
README.md		README.md
RegFile32x64.v		RegFile32x64.v
RegFileTestbench.v		RegFileTestbench.v
RegisterNbit.v		RegisterNbit.v
pll.v		pll.v
quad_7seg_decoder.v		quad_7seg_decoder.v
rom_case.v		rom_case.v

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ARMv8

ARMv8 Processor