fixed typo in file name

RPTU-EIS · Jul 11, 2024 · f61786a · f61786a
1 parent 5e50031
commit f61786a
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Showing 2 changed files with 13 additions and 28 deletions.
diff --git a/src/main/scala/Verilog_Generator.scala b/src/main/scala/Verilog_Generator.scala
@@ -0,0 +1,13 @@
+package main.scala
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+
+import RISCV_TOP._
+
+object VerilogGen extends App
+{
+  emitVerilog(new RISCV_TOP(), Array("--target-dir", "generated-src"))
+}
diff --git a/src/main/scala/Veriolog_Generator.scala b/src/main/scala/Veriolog_Generator.scala