This change refactors the current ROCclr cmake build to accomodate a
more modular approach. This allows easier support for multiple compiler
and/or multiple runtime backends.

Currently supported compilers:
    HSAIL - enabled by ROCCLR_ENABLE_HSAIL (defaults to OFF)
    LC    - enabled by ROCCLR_ENABLE_LC    (defaults to ON)

Currently supported runtimes:
    HSA - enabled by ROCCLR_ENABLE_HSA (defaults to ON)
    PAL - enabled by ROCCLR_ENABLE_PAL (defaults to OFF)

Any configuration is supported as long as at least one compiler and one
runtime is enabled.

Since ROCclr clients can configure it differently, one cannot reuse the
same ROCclr build artifacts between different clients. To assure this,
this patch assumes that ROCclr will be built as part of the clients
project.

Change-Id: Id4a5c43634296802b8ae87d1ad5984968391ccaf

With HIP API callback runtime has to stall the queue until the
callback is done. Rocclr will introduce SW blocking HSA signal,
which will be released after the callback is done.

Change-Id: I6411f3efab31b468e3b87ebb5c8d155e116b613d

Change-Id: I337b8d3b38a492b77b55602ab3a6bb3c05e693e0

Add an extension to memory advise to disable cache coherency for
better performance

Change-Id: I283703d81d9c36ddfa2c8fffa15eef60e2195056

Change-Id: I54ca6e8458cf6414c263df7a8bf61f7ce39a64df

All KMD/asic_reg/UGL headers are located under the drivers folder. No
need for the AMD_UGL_PATH variable as it essentially is
${AMD_DRIVERS_PATH}/ugl.

Change-Id: I070d737d50f2096493b3e75ef9b9e824cb19d048

Switch HSA_AMD_SVM_ATTRIB_READ_ONLY to
HSA_AMD_SVM_ATTRIB_READ_MOSTLY to match Cuda. The new attribute
was just exposed in ROCr/KFD.

Change-Id: I2ee522d33c347ba52a4e272d2cd7f67960490cf7

Change-Id: I132fa424cf9bec608e5c8429e93d20e78b76c6f0

For DD, send a NOP packet so that we leverage the handler to indicate
completion.

Change-Id: Ie57ea0124a8497d39cc49da1c4575c2cd86b9319

Revert back to using the Raven (gfx902) target ID for Raven 2 (gfx909).
This is due to the HSAIL compiler not supporting gfx909.

In theory there should be no issue with running Raven isa on Raven 2.

Change-Id: I425edebc99075799eda5522fad231b8fb3184873

If AMD event contains a reference to a HW event, then runtime
could check/wait for HW event. CPU status update will occur later
after HSA signal callback, but it's not important for the result.

Change-Id: I591391a953bbdba6a25ac07e2cd98aeb17cd4596

Add a Purge function to MemObjMap

Change-Id: Iac51dfda9a7b7c45f2f4a0dc35f7a623121aba1a

…a host ptr

Change-Id: I530eb39104bbe727c3e38186f6db4e64285b3fc8

- Create an env var ROC_ACTIVE_WAIT_TIMEOUT to set active wait timeout
- Record profiling informaion if marker_ts_ property is valid.

Change-Id: If0d8aec8d9b0715027cf0f7c3dc8a4c722a6bae6

Add Navi 24 support

Change-Id: I7343384cf6fb8c532321e57e202c196ef054f459

Change-Id: I9701fbab587e2ea31e58449e8c8b07341a7aa161

Add lock protection for signal processing
If signal is reused, then disable reference to it from HIP
Increase the pool signal size to 32

Change-Id: I7d529b35910f83ce577c9eca6d3386759611ccc0

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Christophe Paquot <[email protected]>
Change-Id: Iff0253a181bbfc1984304014a9e3b542b2556635

Reset hasPendingDispatch_ if we insert barrier for time marker.

Change-Id: Id038fd4e1c910c0a657978fee00630e49c372321

…, MI100 and MI200

Change-Id: I6f07036d8ee6e4c6b55196a13288f8107488d824

Batch marker already has a barrier with HSA signal callback

Change-Id: I69fc63d72320c2e9cc2d2e59ebd3f07c0bd0e3b5

We do not want to release resources during setStatus in HIP because of Graphs

Change-Id: Idc7b188ab5f8be6975ea91005dd2bbf177401f8c

Change-Id: Id5a27034005a7deba37072d8a4c6f250104a96c8

Change-Id: I34d7063f05dd46c32cf59a88c455691ba5099679

Runtime can't assign internal HSA signals for HIP events, because
HIP application can destroy the HIP stream or signal reuse may
occur internally. Switch to global HSA signals for HIP events.

Change-Id: Ieaea2d6b039e492b2e7c5112782a8f4e601e50a1

Change-Id: Iba2f2bb882c4786a432a523cb0954761e5359e7f

Some chunk memory are not guaranteed to be resident during
initial allocation. Use CPDMA to force resident.

Change-Id: If1a2da3e75f136caaa4c7a29d8f604d6af2639fa

Change-Id: I934797bda471618c3f69484a1552b37345ae638b

Change-Id: I40a42d67d2c911d2c9a0bf425f36bc795f9539c0

Change-Id: Id29aacd09d0a9934a027446c57c7095804e1a454

Change-Id: I4ae4c4498765f10c98bb5f2443a083463b0e25af

Change-Id: I2fc1a43c048b4fa1e42f27c4cf5c72fc7ae84e9c

Change-Id: I444ec284669b6a6fff31182e213b47c562c90192

Setting AMD_CPU_AFFINITY=1 will keep Async Handler thread within the
bounds set by numactl.

Change-Id: Id01b30df5127d65c29ac072bf74a04986b7128de

Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261

Change-Id: Iccc0206f3f2c5b3c03f6ed313537f0f364a4ca29

HSA signal calback may occur during the actual marker submit. That
may cause a deadlock, because shared lock_ object. Create the new
notify_lock_ field to protect the notification.

Change-Id: I9752af84e59895530620fac3932c6fc276de8658

Currently ADL is only being included if we build HSAIL and not LC. The
only configuration that does this is Ellesmere on Linux.

As the appprofile logic doesn't do anything right now, it should be
safe to remove it.

Change-Id: I13ce8c27af08c25b95edcbfd2ee1ce447b0bfd39

… ensure ordering before a hipStreamWrite()

Change-Id: I8853ad86a6634d55a98173ca3f79d93b85c08f85

Change-Id: Ib18a53a9016eb5c5ffd51bf6835cba7299ec8421

…s in wrong constructor overload.

Change-Id: I433b70dc70377ae0c5f9b29818703e1ac9d95053

CMake always searches system paths for specified files before resorting
to the hints we give it. We should not be using elf and GL headers
from /usr/include.

Change-Id: I2172ce3da9cc101ced63e22d95ecc031b94f0a67

…mWrite()

Change-Id: Ic2946b68c427d3e058948c0813863a27c21b903d

Add ref counting to ProfilingSignal class to track the last release.
If a signal was used in the marker, then don't reuse it,
but create a new one for internal usage.
Don't rely on HSA callback for the command status update if there
are no pending dispatches.

Change-Id: I19f14ed9d80acfe79993b343b2187635f8428a20

Change-Id: Ie876deb62859f5551f4ed69eb8187ac3fa35f42a

Below logic is causing a crash in the CL-GL interop. As a workaround,
limit it only to HIP.

Change-Id: I12e81d035ebd80a4a9a09eb6eea2fae7040d90c9

Change-Id: Ic6f0ad384404712d5eeb1eaf600e231a8f8631f7

Change-Id: Idea5adf7a4705cb999da6785e6229fe3200dce17

Change-Id: Ic1507cc6d63e9ed574e8e169bce7bf56f4792c19

Change-Id: I1b97a1100e4c498f53aaad7157f21d0c5f8a130d

…rupt"

This reverts commit ce3bf0d.

Reason for revert: need SWDEV-294782 to be resolved before we can enable SQ interrupt support.

Change-Id: I328170b60f1a3aab28c0b1fd3191297a1a51ecb7

… particularly 'value' arg to unsigned 'value

Change-Id: I74b24b2dec911acd5e7a364ea8c050c2ecb1c3b8

- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset

Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041

Only add Roc path and don't use Pal path.

Signed-off-by: Aaron Liu <[email protected]>
Change-Id: I7117e2dc3c3ad4c8d563e9bbdc721f70ddba51fd

Change-Id: I994f3e7c67ed29c4ee46229c8bcd1448fc7f59ec

Change-Id: Iba90a31f9c5d6d4f2b60b7ccf903325c03d4d245

Below logic allocates the host buffer whenever a subbuffer is created
from a SVM allocation. This is only needed for multi-device contexts.

HIP does not support multi-device contexts, hence this logic just ends
up performing unnecessary system allocations.

Change-Id: I8eae635f7c5289c52ef73434218c1658b788a456

Fixes error "All control paths should return a value".

Change-Id: I4718688b55b24862465e15ea0d64b32fa44b3299

Change-Id: I80be39ace9d93347f81ef8acd7858d43bc4a3f1e

…ncl.

Change-Id: I5c28e9c606dec1c956f3f48071d8a0271adfff22

This a cherry pick from the ASIC's branch.

Change-Id: Ic6e888f8fa96103d1e79432dd75e68faabd8cf6c

Change-Id: Ie3ad85a8335b1fc751812c09bb0cd30aad38dcae

Change-Id: Ib9e25a6beb97cc042bb3cc50338686a8dd09e21c

This module will be used to add any specific compiler options to ROCclr
and it's clients.

Currently it only adds a workaround to remove the MSVC flag /GR, which
is added by default CMake <3.20. This resolves the conflict of PAL
adding /GR-.

Change-Id: If83adb271bcec86812a6e9de940da3920fc75393

Note that this requires base driver CL#2340320+ to have SQ interrupt
functionality enabled by default.

Change-Id: I04b936819ebe1eb7cf5de1db4fafe83af3a1b5f6

…hsa_ext_image_descriptor_t

Change-Id: I0af0f09120f15a42349ec4de491df8aee7bfd46d

There is a possible race condition when signal reuse can have
access to a destroyed Timestamp object, because the callback
was running asynchronously. Use reference counter and lock
to allow asynchronous timestamp update

Change-Id: I6224f7c62cb0a03a7466fcc512e5e5afb06736fa