This project contains several different kinds of debouncing circuits done in VHDL.

Following debouncers are implemented:

FSM debouncer: Debouncer made by using FSM. Output is set to input only if it
has been stable for n number of clock cycles.

Rising edge debouncer: Variation of FSM debouncer. In this debouncer, output
goes directly to one when the input signal goes to high, and stays there until
input has been zero for at least the number of clock cycles defined.

Sampling debouncer: Samples the input signal at predetermined intervals. Output
is set to input value when the current sample and the previous sample are same, otherwise
current output value is held.

All files licensed under PUBLIC DOMAIN.