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Mc avx old #1

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@QSXW QSXW commented Jun 6, 2023

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QSXW added 8 commits May 25, 2023 02:39
put_vvc_luma_hv_C:            15480181
put_vvc_luma_hv_16_avx512icl:  1649488

Signed-off-by: Wu Jianhua <[email protected]>
ff_vvc_put_vvc_luma_h_16_C_w4_h4:                846
ff_vvc_put_vvc_luma_h_16_avx512icl_w4_h4:        137
ff_vvc_put_vvc_luma_h_16_C_w8_h8:               1115
ff_vvc_put_vvc_luma_h_16_avx512icl_w8_h8:         80
ff_vvc_put_vvc_luma_h_16_C_w16_h16:             4531
ff_vvc_put_vvc_luma_h_16_avx512icl_w16_h16:      355
ff_vvc_put_vvc_luma_h_16_C_w32_h32:            18828
ff_vvc_put_vvc_luma_h_16_avx512icl_w32_h32:     1271
ff_vvc_put_vvc_luma_h_16_C_w64_h64:            72362
ff_vvc_put_vvc_luma_h_16_avx512icl_w64_h64:     4850
ff_vvc_put_vvc_luma_h_16_C_w128_h128:         288658
ff_vvc_put_vvc_luma_h_16_avx512icl_w128_h128:  19746

Signed-off-by: Wu Jianhua <[email protected]>
ff_vvc_put_vvc_luma_v_16_C_w4_h4:                 399
ff_vvc_put_vvc_luma_v_16_avx512icl_w4_h4:         113
ff_vvc_put_vvc_luma_v_16_C_w8_h8:                1309
ff_vvc_put_vvc_luma_v_16_avx512icl_w8_h8:         171
ff_vvc_put_vvc_luma_v_16_C_w16_h16:              4867
ff_vvc_put_vvc_luma_v_16_avx512icl_w16_h16:       590
ff_vvc_put_vvc_luma_v_16_C_w32_h32:             18842
ff_vvc_put_vvc_luma_v_16_avx512icl_w32_h32:      2235
ff_vvc_put_vvc_luma_v_16_C_w64_h64:             73020
ff_vvc_put_vvc_luma_v_16_avx512icl_w64_h64:      8559
ff_vvc_put_vvc_luma_v_16_C_w128_h128:          286941
ff_vvc_put_vvc_luma_v_16_avx512icl_w128_h128:   34015

Signed-off-by: Wu Jianhua <[email protected]>
ff_vvc_put_vvc_luma_h_16_C_w4_h4:                340
ff_vvc_put_vvc_luma_h_16_avx2_w4_h4:              64
ff_vvc_put_vvc_luma_h_16_C_w8_h8:               1212
ff_vvc_put_vvc_luma_h_16_avx2_w8_h8:             120
ff_vvc_put_vvc_luma_h_16_C_w16_h16:             4684
ff_vvc_put_vvc_luma_h_16_avx2_w16_h16:           386
ff_vvc_put_vvc_luma_h_16_C_w32_h32:            21161
ff_vvc_put_vvc_luma_h_16_avx2_w32_h32:          1381
ff_vvc_put_vvc_luma_h_16_C_w64_h64:            85119
ff_vvc_put_vvc_luma_h_16_avx2_w64_h64:          5236
ff_vvc_put_vvc_luma_h_16_C_w128_h128:         320314
ff_vvc_put_vvc_luma_h_16_avx2_w128_h128:       21994

Signed-off-by: Wu Jianhua <[email protected]>
ff_vvc_put_vvc_luma_hv_16_C_w4_h4:             130368
ff_vvc_put_vvc_luma_hv_16_avx2_w4_h4:           24447
ff_vvc_put_vvc_luma_hv_16_C_w8_h8:             342297
ff_vvc_put_vvc_luma_hv_16_avx2_w8_h8:           36312
ff_vvc_put_vvc_luma_hv_16_C_w16_h16:          1111204
ff_vvc_put_vvc_luma_hv_16_avx2_w16_h16:        140174
ff_vvc_put_vvc_luma_hv_16_C_w32_h32:          4111344
ff_vvc_put_vvc_luma_hv_16_avx2_w32_h32:        550833
ff_vvc_put_vvc_luma_hv_16_C_w64_h64:         15383468
ff_vvc_put_vvc_luma_hv_16_avx2_w64_h64:       2204067
ff_vvc_put_vvc_luma_hv_16_C_w128_h128:       59013947
ff_vvc_put_vvc_luma_hv_16_avx2_w128_h128:     8876216

Signed-off-by: Wu Jianhua <[email protected]>
ff_vvc_put_vvc_luma_v_16_C_w4_h4:              38329
ff_vvc_put_vvc_luma_v_16_avx2_w4_h4:           10133
ff_vvc_put_vvc_luma_v_16_C_w8_h8:             129643
ff_vvc_put_vvc_luma_v_16_avx2_w8_h8:           18627
ff_vvc_put_vvc_luma_v_16_C_w16_h16:           473556
ff_vvc_put_vvc_luma_v_16_avx2_w16_h16:         64610
ff_vvc_put_vvc_luma_v_16_C_w32_h32:          1874001
ff_vvc_put_vvc_luma_v_16_avx2_w32_h32:        251537
ff_vvc_put_vvc_luma_v_16_C_w64_h64:          7247058
ff_vvc_put_vvc_luma_v_16_avx2_w64_h64:        998391
ff_vvc_put_vvc_luma_v_16_C_w128_h128:       28602886
ff_vvc_put_vvc_luma_v_16_avx2_w128_h128:     4017060

Signed-off-by: Wu Jianhua <[email protected]>
ff_vvc_put_vvc_luma_h_8_C_w4_h4:              40440
ff_vvc_put_vvc_luma_h_8_avx2_w4_h4:            3009
ff_vvc_put_vvc_luma_h_8_C_w8_h8:             155320
ff_vvc_put_vvc_luma_h_8_avx2_w8_h8:            5717
ff_vvc_put_vvc_luma_h_8_C_w16_h16:           616144
ff_vvc_put_vvc_luma_h_8_avx2_w16_h16:         18478
ff_vvc_put_vvc_luma_h_8_C_w32_h32:          2462780
ff_vvc_put_vvc_luma_h_8_avx2_w32_h32:         69706
ff_vvc_put_vvc_luma_h_8_C_w64_h64:          9727819
ff_vvc_put_vvc_luma_h_8_avx2_w64_h64:        284385
ff_vvc_put_vvc_luma_h_8_C_w128_h128:       38717268
ff_vvc_put_vvc_luma_h_8_avx2_w128_h128:     1229316

Signed-off-by: Wu Jianhua <[email protected]>
ff_vvc_put_vvc_luma_hv_8_C_w4_h4:             130862
ff_vvc_put_vvc_luma_hv_8_avx2_w4_h4:           16154
ff_vvc_put_vvc_luma_hv_8_C_w8_h8:             344271
ff_vvc_put_vvc_luma_hv_8_avx2_w8_h8:           25723
ff_vvc_put_vvc_luma_hv_8_C_w16_h16:          1134516
ff_vvc_put_vvc_luma_hv_8_avx2_w16_h16:         95782
ff_vvc_put_vvc_luma_hv_8_C_w32_h32:          4038029
ff_vvc_put_vvc_luma_hv_8_avx2_w32_h32:        380669
ff_vvc_put_vvc_luma_hv_8_C_w64_h64:         15027688
ff_vvc_put_vvc_luma_hv_8_avx2_w64_h64:       1500418
ff_vvc_put_vvc_luma_hv_8_C_w128_h128:       58250619
ff_vvc_put_vvc_luma_hv_8_avx2_w128_h128:     6018737

Signed-off-by: Wu Jianhua <[email protected]>
QSXW pushed a commit that referenced this pull request Jan 13, 2024
In close_output(), a dummy frame is created with format NONE passed
to enc_open(), which isn't prepared for it. The NULL pointer
dereference happened at
av_pix_fmt_desc_get(enc_ctx->pix_fmt)->comp[0].depth.

When fgt.graph is NULL, skip fg_output_frame() since there is
nothing to output.

frame #0: 0x0000005555bc34a4 ffmpeg_g`enc_open(opaque=0xb400007efe2db690, frame=0xb400007efe2d9f70) at ffmpeg_enc.c:235:44
frame #1: 0x0000005555bef250 ffmpeg_g`enc_open(sch=0xb400007dde2d4090, enc=0xb400007e4e2daad0, frame=0xb400007efe2d9f70) at ffmpeg_sched.c:1462:11
frame ffvvc#2: 0x0000005555bee094 ffmpeg_g`send_to_enc(sch=0xb400007dde2d4090, enc=0xb400007e4e2daad0, frame=0xb400007efe2d9f70) at ffmpeg_sched.c:1571:19
frame ffvvc#3: 0x0000005555bee01c ffmpeg_g`sch_filter_send(sch=0xb400007dde2d4090, fg_idx=0, out_idx=0, frame=0xb400007efe2d9f70) at ffmpeg_sched.c:2154:12
frame ffvvc#4: 0x0000005555bcf124 ffmpeg_g`close_output(ofp=0xb400007e4e2d85b0, fgt=0x0000007d1790eb08) at ffmpeg_filter.c:2225:15
frame ffvvc#5: 0x0000005555bcb000 ffmpeg_g`fg_output_frame(ofp=0xb400007e4e2d85b0, fgt=0x0000007d1790eb08, frame=0x0000000000000000) at ffmpeg_filter.c:2317:16
frame ffvvc#6: 0x0000005555bc7e48 ffmpeg_g`filter_thread(arg=0xb400007eae2ce7a0) at ffmpeg_filter.c:2836:15
frame ffvvc#7: 0x0000005555bee568 ffmpeg_g`task_wrapper(arg=0xb400007d8e2db478) at ffmpeg_sched.c:2200:21

Signed-off-by: Zhao Zhili <[email protected]>
QSXW pushed a commit that referenced this pull request Dec 23, 2024
Explicitly use ldur for unaligned offsets; newer versions of
armasm64 implicitly convert ldr to ldur as necessary, but older
versions require it explicitly written out.

This fixes these build errors:

    ffmpeg\libavcodec\aarch64\vvc\inter.o.asm(2039) :
     error A2518: operand 2: Memory offset must be aligned
            ldr             s5, [x1, #1]
    ffmpeg\libavcodec\aarch64\vvc\inter.o.asm(2250) :
     error A2518: operand 2: Memory offset must be aligned
            ldr             d7, [x1, ffvvc#2]

Signed-off-by: Martin Storsjö <[email protected]>
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