SystemVerilog Modules

A collection of SystemVerilog modules to take with you in your pocket and learn basic designs of digital electronics

Getting Started

This is an example of how you may give instructions on setting up your project locally. To get a local copy up and running follow this simple step:

Installation

These modules are designed for HDL learning. Once you clone the project, run it in any simulator of your choice.

• Hint: These modules can be simulated online using the free web browser editor/simulator EDA Playgrund

Clone the repo

git clone https://github.com/Phzera/SVmodules.git

Roadmap

• Add ASync FIFO Testbench
• Add MUX
• Add DEMUX
• FSM
  • Mealy
  • Moore
  • ...
• UART
  • TX
  • RX
• Add RAM
• TBD...

-> Continuos improvement with no deadlines...

Contributions and suggestions are welcome!