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feat(frontend): add ClockGate at frontend SRAMTemplate #3889

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merged 2 commits into from
Nov 19, 2024

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Lawrence-ID
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  • Add param withClockGate at SRAMTemplate
  • when SRAM is single-port, use maskedClock for both array.read() and array.write() to ensure single-port SRAM access.
  • when SRAM is multi-port, the read and write ports of the multi-port SRAM are gated using different clocks.

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and array\.write\(\) to ensure single-port SRAM access.
* when SRAM is multi-port, the read and write ports of the multi-port SRAM are gated using different clocks.
@Lawrence-ID Lawrence-ID changed the title feat: add ClockGate at frontend SRAMTemplate feat(frontend): add ClockGate at frontend SRAMTemplate Nov 18, 2024
@Lawrence-ID Lawrence-ID added the power about power design or optimization label Nov 18, 2024
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[Generated by IPC robot]
commit: e335769

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
e335769 1.917 0.450 2.697 1.229 2.840 2.464 2.398 0.920 1.430 2.069 3.432 2.720 2.387 3.261

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
3e2285d 1.917 0.450 2.701 1.226 2.840 2.464 2.398 0.921 1.430 2.069 3.437 2.716 2.387 3.261
c49ebec 1.917 0.450 2.696 1.230 2.840 2.464 2.398 0.920 1.430 2.069 3.432 2.720 2.387 3.261
cfa1639 0.450 2.701 1.244 2.473 2.398 0.915 1.429 1.700 3.470 2.729 3.280
0d13456 1.920 0.450 2.701 1.234 2.891 2.473 2.398 0.915 1.429 1.700 3.470 2.729 2.417 3.280
011f1ef 1.917 0.450 2.701 1.241 2.891 2.473 2.398 0.915 1.429 1.700 3.470 2.729 2.417 3.280

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@eastonman eastonman left a comment

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LGTM

@Gao-Zeyu Gao-Zeyu merged commit 39d5540 into master Nov 19, 2024
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@Gao-Zeyu Gao-Zeyu deleted the frontend-SRAMClockGated branch November 19, 2024 07:41
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5 participants