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fix(LoadQueueReplay): fix enq mask generate when redirect #3884

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merged 1 commit into from
Nov 18, 2024
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fix(LoadQueueReplay): fix enq mask generate when redirect #3884

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10 changes: 6 additions & 4 deletions src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -277,6 +277,7 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
val needEnqueue = VecInit((0 until LoadPipelineWidth).map(w => {
canEnqueue(w) && !cancelEnq(w) && needReplay(w) && !hasExceptions(w)
}))
val newEnqueue = Wire(Vec(LoadPipelineWidth, Bool()))
val canFreeVec = VecInit((0 until LoadPipelineWidth).map(w => {
canEnqueue(w) && loadReplay(w) && (!needReplay(w) || hasExceptions(w))
}))
Expand Down Expand Up @@ -381,7 +382,7 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
val needCancel = Wire(Vec(LoadQueueReplaySize, Bool()))
// generate enq mask
val enqIndexOH = Wire(Vec(LoadPipelineWidth, UInt(LoadQueueReplaySize.W)))
val s0_loadEnqFireMask = io.enq.map(x => x.fire && !x.bits.isLoadReplay && x.bits.rep_info.need_rep).zip(enqIndexOH).map(x => Mux(x._1, x._2, 0.U))
val s0_loadEnqFireMask = newEnqueue.zip(enqIndexOH).map(x => Mux(x._1, x._2, 0.U))
val s0_remLoadEnqFireVec = s0_loadEnqFireMask.map(x => VecInit((0 until LoadPipelineWidth).map(rem => getRemBits(x)(rem))))
val s0_remEnqSelVec = Seq.tabulate(LoadPipelineWidth)(w => VecInit(s0_remLoadEnqFireVec.map(x => x(w))))

Expand Down Expand Up @@ -603,9 +604,10 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
assert(freeList.io.canAllocate.reduce(_ || _) || !io.enq.map(_.valid).reduce(_ || _), s"LoadQueueReplay Overflow")

// Allocate logic
val newEnqueue = (0 until LoadPipelineWidth).map(i => {
needEnqueue(i) && !io.enq(i).bits.isLoadReplay
})
needEnqueue.zip(newEnqueue).zip(io.enq).map {
case ((needEnq, newEnq), enq) =>
newEnq := needEnq && !enq.bits.isLoadReplay
}

for ((enq, w) <- io.enq.zipWithIndex) {
vaddrModule.io.wen(w) := false.B
Expand Down
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