fix(xtval): fix selection of tval for trap

OpenXiangShan · Nov 18, 2024 · 3b733a2 · 3b733a2
1 parent 1035522
commit 3b733a2
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Showing 3 changed files with 12 additions and 17 deletions.
diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
@@ -84,12 +84,10 @@ class TrapEntryHSEventModule(implicit val p: Parameters) extends Module with CSR
   private val tvalFillInst     = isIllegalInst
 
   private val tval = Mux1H(Seq(
-    (tvalFillPc                     ) -> trapPC,
-    (tvalFillPcPlus2                ) -> (trapPC + 2.U),
-    (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA,
-    (tvalFillMemVaddr &&  memIsVirt ) -> trapMemVA,
-    (isLSGuestExcp                  ) -> trapMemVA,
-    (tvalFillInst                   ) -> trapInst,
+    (tvalFillPc                        ) -> trapPC,
+    (tvalFillPcPlus2                   ) -> (trapPC + 2.U),
+    (tvalFillMemVaddr || isLSGuestExcp ) -> trapMemVA,
+    (tvalFillInst                      ) -> trapInst,
   ))
 
   private val tval2 = Mux1H(Seq(

diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
@@ -81,12 +81,10 @@ class TrapEntryMEventModule(implicit val p: Parameters) extends Module with CSRE
   private val tvalFillInst     = isIllegalInst
 
   private val tval = Mux1H(Seq(
-    (tvalFillPc                     ) -> trapPC,
-    (tvalFillPcPlus2                ) -> (trapPC + 2.U),
-    (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA,
-    (tvalFillMemVaddr &&  memIsVirt ) -> trapMemVA,
-    (isLSGuestExcp                  ) -> trapMemVA,
-    (tvalFillInst                   ) -> trapInst,
+    (tvalFillPc                        ) -> trapPC,
+    (tvalFillPcPlus2                   ) -> (trapPC + 2.U),
+    (tvalFillMemVaddr || isLSGuestExcp ) -> trapMemVA,
+    (tvalFillInst                      ) -> trapInst,
   ))
 
   private val tval2 = Mux1H(Seq(

diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
@@ -92,11 +92,10 @@ class TrapEntryVSEventModule(implicit val p: Parameters) extends Module with CSR
   private val tvalFillInst     = isIllegalInst
 
   private val tval = Mux1H(Seq(
-    (tvalFillPc                     ) -> trapPC,
-    (tvalFillPcPlus2                ) -> (trapPC + 2.U),
-    (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA,
-    (tvalFillMemVaddr &&  memIsVirt ) -> trapMemVA,
-    (tvalFillInst                   ) -> trapInst,
+    tvalFillPc       -> trapPC,
+    tvalFillPcPlus2  -> (trapPC + 2.U),
+    tvalFillMemVaddr -> trapMemVA,
+    tvalFillInst     -> trapInst,
   ))
 
   private val instrAddrTransType = AddrTransType(