Skip to content

Commit

Permalink
rebase to master
Browse files Browse the repository at this point in the history
  • Loading branch information
Lawrence-ID committed Nov 18, 2024
2 parents c0bf3f4 + cfa1639 commit 062e926
Show file tree
Hide file tree
Showing 186 changed files with 10,883 additions and 6,896 deletions.
17 changes: 13 additions & 4 deletions .github/workflows/emu.yml
Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,12 @@ jobs:
- name: V Extension Test - rvv-bench
run: |
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --numa --ci rvv-bench 2> /dev/zero
- name: F16 Test - f16_test
run: |
python3 ./scripts/xiangshan.py --wave-dump ./build --thread 16 --numa --ci f16_test 2> /dev/zero
- name: Zcb Extension Test - zcb-test
run: |
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --numa --ci zcb-test 2> /dev/zero
emu-chi:
runs-on: bosc
needs: changes
Expand Down Expand Up @@ -272,13 +278,13 @@ jobs:
--num-cores 2 --emu-optimize "" \
--dramsim3 /nfs/home/share/ci-workloads/DRAMsim3 \
--with-dramsim3 --threads 16 \
--pgo /nfs/home/share/ci-workloads/linux-hello-smp-newcsr/bbl.bin --llvm-profdata llvm-profdata
--pgo /nfs/home/share/ci-workloads/linux-hello-smp-new/bbl.bin --llvm-profdata llvm-profdata
- name: MC Test
run: |
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --numa --diff ./ready-to-run/riscv64-nemu-interpreter-dual-so --ci mc-tests 2> /dev/zero
- name: SMP Linux
run: |
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --numa --diff ./ready-to-run/riscv64-nemu-interpreter-dual-so --ci linux-hello-smp-newcsr 2> /dev/null
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --numa --diff ./ready-to-run/riscv64-nemu-interpreter-dual-so --ci linux-hello-smp-new 2> /dev/null
simv-basics:
runs-on: eda
needs: changes
Expand Down Expand Up @@ -315,9 +321,12 @@ jobs:
- name: V Extension Test - rvv-test
run: |
ssh -tt eda01 "python3 `echo $GITHUB_WORKSPACE`/scripts/xiangshan.py --wave-dump `echo $WAVE_HOME` --ci-vcs rvv-test"
- name: Simple Test - MicroBench
- name: Simple Test - CoreMark 1 iteration
run: |
ssh -tt eda01 "python3 `echo $GITHUB_WORKSPACE`/scripts/xiangshan.py --wave-dump `echo $WAVE_HOME` --ci-vcs microbench --am=/nfs/home/share/ci-workloads/nexus-am/"
ssh -tt eda01 "python3 `echo $GITHUB_WORKSPACE`/scripts/xiangshan.py --wave-dump `echo $WAVE_HOME` --ci-vcs coremark-1-iteration"
# - name: Simple Test - MicroBench
# run: |
# ssh -tt eda01 "python3 `echo $GITHUB_WORKSPACE`/scripts/xiangshan.py --wave-dump `echo $WAVE_HOME` --ci-vcs microbench --am=/nfs/home/share/ci-workloads/nexus-am/"
# - name: Basic Test - cputest
# run: |
# ssh -tt eda01 "python3 `echo $GITHUB_WORKSPACE`/scripts/xiangshan.py --ci-vcs cputest --am=/nfs/home/share/ci-workloads/nexus-am/" 2> /dev/zero
Expand Down
27 changes: 27 additions & 0 deletions .github/workflows/format.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
name: Format Checking

on:
push:
branches: [ master ]
pull_request:
branches: [ master ]

jobs:
scalafmt:
runs-on: ubuntu-latest
continue-on-error: true
timeout-minutes: 900
name: Check Format
steps:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- uses: actions/setup-java@v4
with:
distribution: 'temurin'
java-version: '11'
- run: |
mkdir ~/.local/bin
sh -c "curl -L https://github.com/com-lihaoyi/mill/releases/download/0.11.7/0.11.7 > ~/.local/bin/mill && chmod +x ~/.local/bin/mill"
export PATH=~/.local/bin:$PATH
- run: make check-format
91 changes: 70 additions & 21 deletions .github/workflows/perf.yml
Original file line number Diff line number Diff line change
Expand Up @@ -2,24 +2,60 @@ name: Performance Regression
on:
schedule:
#run at 15:30 UTC (23:30 UTC+8) on Friday
# - cron: '30 15 * * 5'
- cron: '30 15 * * 5'
#run at 15:30 UTC (23:30 UTC+8) Every two weeks
- cron: '30 15 13,27 * *'
# - cron: '30 15 13,27 * *'
#run it manually when the workflow is in the default branch
workflow_dispatch:
inputs:
test_commit:
description: 'Commit SHA to run the workflow on'
required: false
default: ''
#only for test push
# push:
# branches: [ ci-perf-yml ]


jobs:
run:
runs-on: node
runs-on: perf
continue-on-error: false
#At most 2 days to finish
timeout-minutes: 2880
name: Performance Regression - Checkpoints
name: Checkpoints
steps:
- uses: actions/checkout@v2
- name: Set test commit
id: set_test_commit
run: |
if [ "${{ github.event.inputs.test_commit }}" = "" ]; then
echo "Using latest commit."
echo "commit_sha=${{ github.sha }}" >> $GITHUB_OUTPUT
else
echo "Using specified commit: ${{ github.event.inputs.test_commit }}"
echo "commit_sha=${{ github.event.inputs.test_commit }}" >> $GITHUB_OUTPUT
fi
- name: Determine if this is the biweekly run
id: determine_run
run: |
if [ "${{ github.event_name }}" = "workflow_dispatch" ]; then
echo "run_biweekly=true" >> $GITHUB_OUTPUT
elif [ $(( $(date +'%V') % 2 )) -eq 1 ]; then
echo "run_biweekly=true" >> $GITHUB_OUTPUT
else
echo "run_biweekly=false" >> $GITHUB_OUTPUT
fi
- name: Checkout code at specific commit
if: steps.determine_run.outputs.run_biweekly == 'true'
uses: actions/checkout@v2
with:
ref: ${{ steps.set_test_commit.outputs.commit_sha }}
submodules: 'recursive'

- name: Set env
if: steps.determine_run.outputs.run_biweekly == 'true'
run: |
SHORT_SHA=$(git rev-parse --short HEAD)
DATE=$(git show -s --format=%cd --date=format:%y%m%d HEAD)
Expand All @@ -28,42 +64,55 @@ jobs:
echo "AM_HOME=/nfs/home/share/ci-workloads/nexus-am" >> $GITHUB_ENV
echo "PERF_HOME=/nfs/home/share/ci-workloads/env-scripts/perf" >> $GITHUB_ENV
echo "SPEC_DIR=/nfs/home/ci-runner/master-perf-report/cr${DATE}-${SHORT_SHA}" >> $GITHUB_ENV
- name: Clean up
echo "CKPT_HOME=/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0" >> $GITHUB_ENV
echo "CKPT_JSON_PATH=/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0/cluster-0-0.json" >> $GITHUB_ENV
- name: Clean Up
if: steps.determine_run.outputs.run_biweekly == 'true'
run: |
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
- name: Build EMU with DRAMsim3
if: steps.determine_run.outputs.run_biweekly == 'true'
run: |
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
--dramsim3 /nfs/home/share/ci-workloads/DRAMsim3 \
--with-dramsim3 --threads 16 \
--pgo $GITHUB_WORKSPACE/ready-to-run/coremark-2-iteration.bin \
--llvm-profdata llvm-profdata
if [ -e "$SPEC_DIR/emu" ]; then
mkdir -p $NOOP_HOME/build
cp $SPEC_DIR/emu $NOOP_HOME/build/emu
else
python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
--dramsim3 /nfs/home/share/ci-workloads/DRAMsim3 \
--with-dramsim3 --threads 16 \
--pgo $GITHUB_WORKSPACE/ready-to-run/coremark-2-iteration.bin \
--llvm-profdata llvm-profdata
mkdir -p $SPEC_DIR
cp $NOOP_HOME/build/emu $SPEC_DIR/emu
fi
- name: Run SPEC CPU2006 checkpoints
if: steps.determine_run.outputs.run_biweekly == 'true'
run: |
cd $PERF_HOME
python3 xs_autorun_multiServer.py \
/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0 \
/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0/cluster-0-0.json \
python3 xs_autorun_multiServer.py $CKPT_HOME $CKPT_JSON_PATH \
--xs $NOOP_HOME --threads 16 --dir $SPEC_DIR --resume \
-L "node033 node034 node036 node037 node038 node039 node040 node041 node042"
mv $NOOP_HOME/*.vcd $SPEC_DIR
find $NOOP_HOME/build/ -maxdepth 1 -name "*.vcd" -exec mv {} $SPEC_DIR \;
- name: Report SPEC CPU2006 score
if: steps.determine_run.outputs.run_biweekly == 'true'
run: |
cd $PERF_HOME
python3 xs_autorun_multiServer.py \
/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0 \
/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0/cluster-0-0.json \
python3 xs_autorun_multiServer.py $CKPT_HOME $CKPT_JSON_PATH \
--xs $NOOP_HOME --threads 16 --dir $SPEC_DIR \
--check --dump-json-path $SPEC_DIR/err_ckps.json
python3 xs_autorun_multiServer.py \
/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0 \
/nfs/home/share/checkpoints_profiles/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0/cluster-0-0.json \
python3 xs_autorun_multiServer.py $CKPT_HOME $CKPT_JSON_PATH \
--xs $NOOP_HOME --threads 16 --dir $SPEC_DIR --report \
> $SPEC_DIR/score.txt
mkdir $GITHUB_WORKSPACE/result
cp $SPEC_DIR/err_ckps.json $GITHUB_WORKSPACE/result/err_ckps.json
cp $SPEC_DIR/score.txt $GITHUB_WORKSPACE/result/score.txt
- name: Upload result
if: steps.determine_run.outputs.run_biweekly == 'true'
uses: actions/upload-artifact@v4
with:
name: result
Expand Down
26 changes: 26 additions & 0 deletions .scalafmt.conf
Original file line number Diff line number Diff line change
@@ -0,0 +1,26 @@
version = 3.8.1
runner.dialect = scala213
maxColumn = 120
preset = defaultWithAlign

align.tokens."+" = [{
code = ":"
}]

newlines.source = keep
newlines.afterCurlyLambdaParams = squash

rewrite.rules = [
RedundantBraces,
RedundantParens,
SortModifiers,
Imports
]
rewrite.redundantBraces.generalExpressions = false
rewrite.imports.expand = true
rewrite.imports.sort = scalastyle
rewrite.trailingCommas.style = never

docstrings.style = keep

project.includePaths = ["glob:**/src/main/scala/xiangshan/frontend/**.scala"]
14 changes: 9 additions & 5 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ MEM_GEN_SEP = ./scripts/gen_sep_mem.sh

CONFIG ?= DefaultConfig
NUM_CORES ?= 1
ISSUE ?= B
ISSUE ?= E.b

SUPPORT_CHI_ISSUE = B E.b
ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),)
Expand Down Expand Up @@ -113,12 +113,9 @@ override SIM_ARGS += --with-constantin
endif

# emu for the release version
RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen
RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem
DEBUG_ARGS += --enable-difftest
PLDM_ARGS += --fpga-platform --enable-difftest
ifeq ($(GOALS),verilog)
RELEASE_ARGS += --disable-always-basic-diff
endif
ifeq ($(RELEASE),1)
override SIM_ARGS += $(RELEASE_ARGS)
else ifeq ($(PLDM),1)
Expand Down Expand Up @@ -201,6 +198,7 @@ clean:
init:
git submodule update --init
cd rocket-chip && git submodule update --init cde hardfloat
cd openLLC && git submodule update --init openNCB

bump:
git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
Expand All @@ -211,6 +209,12 @@ bsp:
idea:
mill -i mill.idea.GenIdea/idea

check-format:
mill xiangshan.checkFormat

reformat:
mill xiangshan.reformat

# verilator simulation
emu: sim-verilog
$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
Expand Down
8 changes: 4 additions & 4 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ Copyright 2020-2022 by Peng Cheng Laboratory.

## Docs and slides

[XiangShan-doc](https://github.com/OpenXiangShan/XiangShan-doc) is our official documentation repository. It contains design spec., technical slides, tutorial and more.
[XiangShan-doc](https://github.com/OpenXiangShan/XiangShan-doc) is our official documentation repository. It contains design spec., technical slides, tutorials and more.

* Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io

Expand Down Expand Up @@ -38,13 +38,13 @@ Zhihu/知乎:[香山开源处理器](https://www.zhihu.com/people/openxiangsha

Weibo/微博:[香山开源处理器](https://weibo.com/u/7706264932)

You can contact us through [our mail list](mailto:[email protected]). All mails from this list will be archived to [here](https://www.mail-archive.com/[email protected]/).
You can contact us through [our mailing list](mailto:[email protected]). All mails from this list will be archived [here](https://www.mail-archive.com/[email protected]/).

## Architecture

The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) [on the yanqihu branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020.
The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) and is [on the yanqihu branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020.

The second stable micro-architecture of XiangShan is called Nanhu (南湖) [on the nanhu branch](https://github.com/OpenXiangShan/XiangShan/tree/nanhu).
The second stable micro-architecture of XiangShan is called Nanhu (南湖) and is [on the nanhu branch](https://github.com/OpenXiangShan/XiangShan/tree/nanhu).

The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.

Expand Down
37 changes: 36 additions & 1 deletion build.sc
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@

import mill._
import scalalib._
import scalafmt._
import $file.`rocket-chip`.common
import $file.`rocket-chip`.cde.common
import $file.`rocket-chip`.hardfloat.build
Expand All @@ -27,6 +28,7 @@ import $file.openLLC.common
/* for publishVersion */
import $ivy.`de.tototec::de.tobiasroeser.mill.vcs.version::0.4.0`
import de.tobiasroeser.mill.vcs.version.VcsVersion
import java.io.{BufferedReader, InputStreamReader}
import java.time.LocalDateTime
import java.time.format.DateTimeFormatter
import java.util.Locale
Expand Down Expand Up @@ -143,6 +145,16 @@ object coupledL2 extends millbuild.coupledL2.common.CoupledL2Module with HasChis

}

object openNCB extends SbtModule with HasChisel {

override def millSourcePath = os.pwd / "openLLC" / "openNCB"

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip
)

}

object openLLC extends millbuild.openLLC.common.OpenLLCModule with HasChisel {

override def millSourcePath = os.pwd / "openLLC"
Expand All @@ -152,6 +164,9 @@ object openLLC extends millbuild.openLLC.common.OpenLLCModule with HasChisel {
def rocketModule: ScalaModule = rocketchip

def utilityModule: ScalaModule = utility

def openNCBModule: ScalaModule = openNCB

}

object difftest extends HasChisel {
Expand Down Expand Up @@ -216,7 +231,7 @@ trait XiangShanModule extends ScalaModule {
override def forkEnv = Map("PATH" -> envPATH)
}

object xiangshan extends XiangShanModule with HasChisel {
object xiangshan extends XiangShanModule with HasChisel with ScalafmtModule {

override def millSourcePath = os.pwd

Expand Down Expand Up @@ -263,8 +278,28 @@ object xiangshan extends XiangShanModule with HasChisel {
LocalDateTime.now().format(DateTimeFormatter.ofPattern("MMM dd hh:mm:ss yyyy").withLocale(new Locale("en")))),
)

def gitStatus: T[String] = {
val gitRevParseBuilder = new ProcessBuilder("git", "rev-parse", "HEAD")
val gitRevParseProcess = gitRevParseBuilder.start()
val shaReader = new BufferedReader(new InputStreamReader(gitRevParseProcess.getInputStream))
val sha = shaReader.readLine()

val gitStatusBuilder = new ProcessBuilder("git", "status", "-uno", "--porcelain")
val gitStatusProcess = gitStatusBuilder.start()
val gitStatusReader = new BufferedReader(new InputStreamReader(gitStatusProcess.getInputStream))
val status = gitStatusReader.readLine()
val gitDirty = if (status == null) 0 else 1

val str =
s"""|SHA=$sha
|dirty=$gitDirty
|""".stripMargin
str
}

override def resources = T.sources {
os.write(T.dest / "publishVersion", publishVersion())
os.write(T.dest / "gitStatus", gitStatus())
super.resources() ++ Seq(PathRef(T.dest))
}

Expand Down
2 changes: 1 addition & 1 deletion coupledL2
Submodule coupledL2 updated 29 files
+31 −34 Makefile
+1 −1 src/main/scala/coupledL2/BaseSlice.scala
+2 −0 src/main/scala/coupledL2/Common.scala
+15 −5 src/main/scala/coupledL2/CoupledL2.scala
+19 −11 src/main/scala/coupledL2/DataStorage.scala
+2 −0 src/main/scala/coupledL2/L2Param.scala
+2 −2 src/main/scala/coupledL2/MSHRBuffer.scala
+1 −1 src/main/scala/coupledL2/RequestArb.scala
+7 −5 src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala
+2 −2 src/main/scala/coupledL2/tl2chi/MMIOBridge.scala
+85 −41 src/main/scala/coupledL2/tl2chi/MSHR.scala
+26 −1 src/main/scala/coupledL2/tl2chi/MSHRCtl.scala
+30 −6 src/main/scala/coupledL2/tl2chi/MainPipe.scala
+4 −3 src/main/scala/coupledL2/tl2chi/RXSNP.scala
+5 −0 src/main/scala/coupledL2/tl2chi/Slice.scala
+47 −58 src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala
+5 −2 src/main/scala/coupledL2/tl2chi/TXDAT.scala
+3 −0 src/main/scala/coupledL2/tl2chi/TXREQ.scala
+4 −1 src/main/scala/coupledL2/tl2chi/TXRSP.scala
+16 −16 src/main/scala/coupledL2/tl2chi/chi/AsyncBridge.scala
+12 −4 src/main/scala/coupledL2/tl2chi/chi/CHILogger.scala
+17 −13 src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala
+134 −0 src/main/scala/coupledL2/tl2chi/chi/Message.scala
+2 −1 src/main/scala/coupledL2/tl2chi/chi/NetworkLayer.scala
+26 −1 src/main/scala/coupledL2/tl2tl/MSHRCtl.scala
+28 −4 src/main/scala/coupledL2/tl2tl/MainPipe.scala
+5 −0 src/main/scala/coupledL2/tl2tl/Slice.scala
+125 −174 src/test/scala/chi/TestTop.scala
+1 −1 utility
2 changes: 1 addition & 1 deletion ready-to-run
Loading

0 comments on commit 062e926

Please sign in to comment.