fix(xtval): fix selection of tval for trap #9218

Sign in to view logs

Run time

Learn about OS pricing on GitHub Actions

Job	Run time
Changes Detection	4s
Generate Verilog	1h 54m 23s
EMU - Basics	3h 0m 54s
EMU - MC	4h 41m 17s
EMU - CHI	1h 26m 28s
EMU - Performance	3h 42m 12s
SIMV - Basics	4h 50m 56s
	19h 36m 14s