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Initial support for Verilog output #2

Open

udif wants to merge 1 commit into MicroTCA-Tech-Lab:master from udif:pr_verilog

udif commented Sep 29, 2020

code passes Verilator compilation without warnings, but not tested.


Initial support for Verilog output

0802c26

code passes Verilator compilation without warnings, but not tested.

udif mentioned this pull request

Synthesizable RTL export SystemRDL/systemrdl-compiler#60

Closed

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