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Switch from pulp-platform/cva6 to MaistoV/cva6_fork

* Bump axi to v0.39.0
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@MaistoV
MaistoV committed Sep 12, 2023
1 parent 8dcd5b3 commit 25cd02e
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6 changes: 3 additions & 3 deletions .gitmodules
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Expand Up @@ -21,9 +21,6 @@
[submodule "hardware/deps/common_verification"]
path = hardware/deps/common_verification
url = https://github.com/pulp-platform/common_verification.git
[submodule "hardware/deps/cva6"]
path = hardware/deps/cva6
url = https://github.com/pulp-platform/cva6.git
[submodule "toolchain/newlib"]
path = toolchain/newlib
url = https://sourceware.org/git/newlib-cygwin.git
Expand All @@ -35,3 +32,6 @@
[submodule "hardware/deps/apb"]
path = hardware/deps/apb
url = https://github.com/pulp-platform/apb.git
[submodule "hardware/deps/cva6"]
path = hardware/deps/cva6
url = [email protected]:MaistoV/cva6_fork.git
2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -10,7 +10,7 @@ package:
dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rerebase }
cva6: { git: "https://github.com/MaistoV/cva6_fork.git", rev: ara_cheshire }
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.1 }
apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 }

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2 changes: 1 addition & 1 deletion hardware/deps/axi
Submodule axi updated 88 files
+74 −13 .ci/Memora.yml
+16 −32 .github/workflows/doc.yml
+12 −67 .github/workflows/gitlab-ci.yml
+2 −0 .gitignore
+40 −8 .gitlab-ci.yml
+48 −6 Bender.yml
+268 −0 CHANGELOG.md
+90 −0 Makefile
+75 −38 README.md
+1 −1 VERSION
+86 −3 axi.core
+264 −0 doc/svg/axi_id_remap_table.svg
+115 −1 include/axi/assign.svh
+50 −16 include/axi/typedef.svh
+6 −2 ips_list.yml
+264 −0 scripts/axi_dumper_interpret.py
+1 −1 scripts/compile_vsim.sh
+6 −0 scripts/run_verilator.sh
+126 −6 scripts/run_vsim.sh
+9 −0 scripts/update_authors
+16 −16 src/axi_atop_filter.sv
+27 −28 src/axi_burst_splitter.sv
+585 −0 src/axi_bus_compare.sv
+1 −3 src/axi_cdc.sv
+23 −3 src/axi_cdc_dst.sv
+24 −5 src/axi_cdc_src.sv
+235 −0 src/axi_chan_compare.sv
+38 −38 src/axi_cut.sv
+19 −19 src/axi_delayer.sv
+181 −657 src/axi_demux.sv
+633 −0 src/axi_demux_simple.sv
+215 −0 src/axi_dumper.sv
+29 −18 src/axi_dw_downsizer.sv
+18 −9 src/axi_dw_upsizer.sv
+11 −11 src/axi_err_slv.sv
+256 −0 src/axi_fifo.sv
+124 −0 src/axi_from_mem.sv
+661 −0 src/axi_id_remap.sv
+454 −0 src/axi_id_serialize.sv
+24 −0 src/axi_intf.sv
+194 −53 src/axi_isolate.sv
+350 −0 src/axi_iw_converter.sv
+121 −0 src/axi_lfsr.sv
+148 −55 src/axi_lite_demux.sv
+567 −0 src/axi_lite_dw_converter.sv
+247 −0 src/axi_lite_from_mem.sv
+223 −0 src/axi_lite_lfsr.sv
+89 −23 src/axi_lite_mux.sv
+4 −4 src/axi_lite_to_axi.sv
+93 −26 src/axi_lite_xbar.sv
+48 −48 src/axi_multicut.sv
+78 −2 src/axi_mux.sv
+123 −11 src/axi_pkg.sv
+110 −0 src/axi_rw_join.sv
+111 −0 src/axi_rw_split.sv
+19 −14 src/axi_serializer.sv
+224 −15 src/axi_sim_mem.sv
+185 −0 src/axi_slave_compare.sv
+568 −56 src/axi_test.sv
+102 −0 src/axi_throttle.sv
+4 −5 src/axi_to_axi_lite.sv
+678 −0 src/axi_to_detailed_mem.sv
+213 −0 src/axi_to_mem.sv
+435 −0 src/axi_to_mem_banked.sv
+249 −0 src/axi_to_mem_interleaved.sv
+261 −0 src/axi_to_mem_split.sv
+164 −51 src/axi_xbar.sv
+256 −0 src/axi_xp.sv
+25 −1 src_files.yml
+215 −13 test/axi_synth_bench.sv
+310 −0 test/tb_axi_bus_compare.sv
+6 −0 test/tb_axi_delayer.sv
+1 −0 test/tb_axi_dw_downsizer.sv
+1 −1 test/tb_axi_dw_pkg.sv
+1 −0 test/tb_axi_dw_upsizer.sv
+199 −0 test/tb_axi_fifo.sv
+201 −0 test/tb_axi_fifo.wave.do
+443 −0 test/tb_axi_iw_converter.sv
+452 −0 test/tb_axi_lite_dw_converter.sv
+1 −0 test/tb_axi_lite_regs.sv
+1 −1 test/tb_axi_lite_to_axi.sv
+11 −42 test/tb_axi_lite_xbar.sv
+5 −5 test/tb_axi_serializer.sv
+37 −29 test/tb_axi_sim_mem.sv
+241 −0 test/tb_axi_slave_compare.sv
+418 −0 test/tb_axi_to_mem_banked.sv
+152 −144 test/tb_axi_xbar.sv
+6 −3 test/tb_axi_xbar_pkg.sv
2 changes: 1 addition & 1 deletion hardware/deps/cva6
Submodule cva6 updated 1 files
+23 −1 common/local/util/instr_trace_item.svh
4 changes: 2 additions & 2 deletions hardware/src/vlsu/vlsu.sv
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Expand Up @@ -89,8 +89,8 @@ module vlsu import ara_pkg::*; import rvv_pkg::*; #(
.aw_chan_t(axi_aw_t ),
.w_chan_t (axi_w_t ),
.b_chan_t (axi_b_t ),
.req_t (axi_req_t ),
.resp_t (axi_resp_t)
.axi_req_t (axi_req_t ),
.axi_resp_t(axi_resp_t)
) i_axi_cut (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
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