fix buffered uart plumbing #798

MEGA65 · Apr 3, 2024 · a5a03c6 · a5a03c6
1 parent 0410d75
commit a5a03c6
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/vhdl/nexys4.vhdl b/src/vhdl/nexys4.vhdl
@@ -581,8 +581,8 @@ begin
       uart_rx => jclo(1),
       uart_tx => jclo(2),
 
-      buffereduart_rx => jalo(1),
-      buffereduart_tx => jalo(2),
+      buffereduart_rx(0) => jalo(1),
+      buffereduart_tx(0) => jalo(2),
 --      buffereduart2_rx => jchi(9),
 --      buffereduart2_tx => jchi(10),
       buffereduart_ringindicate => (others => '0'),