It remians a challenge to develop irregular applications like graph processing algorithms on FPGA using high level synthesis tools. In this work, we take BFS as an example to explore the use of SDAccel for irregular applications. In particular, channels and data flows with undeterministic amount of data are investigated in the examples.
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Liu-Cheng/bfs-using-vivado-hls
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BFS design and optimization using Vivado HLS in SDAccel.
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