RTL-to-GDSII-ASIC-design-of-Counter

The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK). The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

RTL and Simulation

Verilog code for the counter module

`timescale 1ns/1ns
module counter(clk,m,rst,count);
input clk,m,rst;
output reg[7:0]count;
always@(posedge clk or negedge rst)
 begin
  if(!rst)
  count=0;
   else if(m)
   count = count+1;
  else
   count = count-1;
 end
endmodule

Testbench code for the counter module

`timescale 1ns/1ns
module counter_test;
reg clk,rst,m;
wire[7:0]count;
initial
	begin
	 clk=0; rst=0; 
	 #5; rst=1;
	end
initial
	begin
	m=1;
	#160; m=0; //till #160ns - up_counter after it will be down_counter
	end

counter counter1(clk,m,rst,count);
always #5 clk = ~clk;

initial $monitor("Time=%t rst=%b clk=%b m=%b count=%b", $time,rst,clk,m,count);
//$monitor will display the simulation results on the screen
initial
	#320 $finish;
endmodule

To run simulations for the module, use the Xcelium tool with the following command:

irun/xrun module_name.v module_test_name.v -access +rwc -gui

irun counter.v counter_test.v -access +rwc -gui

The simulation output and waveform results were generated as shown below:

Synthesis

The process of converting rtl code into gate-level netlist. It involves 3 stages - translation, mapping, and optimization.

Inputs - 1. verilog file (counter.v) 2. constraints.sdc file 3. library file (.lib)

Outputs - 1. Gate-level netlist 2. Tool constraints file 3. Reports - gates, power, timing, cells...

to run the script file invoke the genus synthesis tool by using the command:

genus

source run.tcl

set_db init_lib_search_path /cad/FOUNDRY/digital/90nm/dig/lib

#set_attribute lef_library /cad/FOUNDRY/digital/90nm/dig/lef/gsclib090_tech.lef

set_db library  slow.lib

read_hdl {./counter.v}

elaborate

read_sdc ./constraints_input.sdc

set_db syn_generic_effort medium
set_db syn_map_effort  medium
set_db syn_opt_effort  medium

syn_generic
syn_map
syn_opt

write_hdl > counter_netlist.vconsta
write_sdc  > counter_tool.sdc

gui_show

report timing > counter_timing.rpt
report power > counter_power.rpt
report area > counter_cell.rpt
report gates > counter_gates.rpt

Physical Design

Invoke the innovus tool using the command

innovus

Creating the Multi-Mode Multi-Corner (MMMC) scenarios for the timing analysis

floorplan

powerplan

placement

clock tree synthesis

#90nm technology
#clock tree constraints used for building and balancing the clock tree in cts stage

##creating_NDR rules:
add_ndr -width {Metal1 0.24 Metal2 0.28 Metal3 0.28 Metal4 0.28 Metal5 0.28 Metal6 0.28 Metal7 0.28 Metal8 0.88 Metal9 0.88} -spacing {Metal1 0.24 Metal2 0.28 Metal3 0.28 Metal4 0.28 Metal5 0.28 Metal6 0.28 Metal7 0.28 Metal8 0.88 Metal9 0.88} -name 2w2s

#create a route type to define the NDR & layers to use for routing the clock tree:
create_route_type -name clkroute -non_default_rule 2w2s -bottom_preferred_layer Metal5 -top_preferred_layer Metal6

##specify this route type should be used for trunk and leaf nets:
set_ccopt_property route_type clkroute -net_type trunk
set_ccopt_property route_type clkroute -net_type leaf

##specify the clock buffer, clock inverter & clock gating cells to use
set_ccopt_property buffer_cells {CLKBUFX6 CLKBUFX8 CLKBUFX12}
set_ccopt_property inverter_cells {CLKINVX6 CLKINVX8 CLKINVX12}
set_ccopt_property clock_gating_cells TLATNTSCA*

##generate the ccopt spec file & source it
create_ccopt_clock_tree_spec -file ccopt.spec
source ccopt.spec

#run ccopt-cts
ccopt_design -cts

##generate reports for clock tree and skew groups
report_ccopt_clock_trees -file clk_trees.rpt
report_ccopt_skew_groups -file skew_groups.rpt

#save the design
saveDesign DBS/cts.enc

routing

rc extraction

physical verification